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fix(driver_spi): move macro GPIO_MATRIX_DELAY_NS out from soc.h
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -313,7 +313,7 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
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/**
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* Reset SPI CPU TX FIFO
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*
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* On ESP32C3, this function is not separated
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* On ESP32C2, this function is not separated
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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@@ -326,7 +326,7 @@ static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
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/**
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* Reset SPI CPU RX FIFO
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*
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* On ESP32C3, this function is not separated
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* On ESP32C2, this function is not separated
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*
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* @param hw Beginning address of the peripheral registers.
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*/
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@@ -859,7 +859,7 @@ static inline void spi_ll_master_set_cs_hold(spi_dev_t *hw, int hold)
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/**
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* Set the delay of SPI clocks before the first SPI clock after the CS active edge.
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*
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* Note ESP32 doesn't support to use this feature when command/address phases
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* Note ESP32C2 doesn't support to use this feature when command/address phases
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* are used in full duplex mode.
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*
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* @param hw Beginning address of the peripheral registers.
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