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I2C: Fix SCL period timings on ESP targets

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The output frequency is now more accurate as the SCL period timings have been fixed.
This fix applies for ESP32, ESP32S3, ESP32C3, ESP32C2 and ESP32H2
This commit is contained in:
Omar Chebib
2022-05-05 14:43:36 +08:00
parent 0adb814af3
commit 477bc9e64c
6 changed files with 68 additions and 73 deletions
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32
components/hal/esp32c3/include/hal/i2c_ll.h
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@@ -1,16 +1,8 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for I2C register operations
@@ -159,17 +151,17 @@ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_clk_cal_t *bus_cfg)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, bus_cfg->clkm_div - 1);
//scl period
hw->scl_low_period.period = bus_cfg->scl_low - 1;
hw->scl_high_period.period = bus_cfg->scl_high;
hw->scl_low_period.period = bus_cfg->scl_low - 2;
hw->scl_high_period.period = bus_cfg->scl_high - 3;
//sda sample
hw->sda_hold.time = bus_cfg->sda_hold;
hw->sda_sample.time = bus_cfg->sda_sample;
hw->sda_hold.time = bus_cfg->sda_hold - 1;
hw->sda_sample.time = bus_cfg->sda_sample - 1;
//setup
hw->scl_rstart_setup.time = bus_cfg->setup;
hw->scl_stop_setup.time = bus_cfg->setup;
hw->scl_rstart_setup.time = bus_cfg->setup - 1;
hw->scl_stop_setup.time = bus_cfg->setup - 1;
//hold
hw->scl_start_hold.time = bus_cfg->hold - 1;
hw->scl_stop_hold.time = bus_cfg->hold;
hw->scl_stop_hold.time = bus_cfg->hold - 1;
hw->timeout.time_out_value = bus_cfg->tout;
hw->timeout.time_out_en = 1;
}