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Merge branch 'feature/config_spi_pins_based_on_efuse_value_v3.3' into 'release/v3.3'
feat(psram): config SPI psram pins based on efuse value (backport v3.3) See merge request espressif/esp-idf!5240
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@@ -48,6 +48,7 @@
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#include "bootloader_random.h"
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#include "bootloader_config.h"
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#include "bootloader_clock.h"
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#include "bootloader_common.h"
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#include "flash_qio_mode.h"
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@@ -61,7 +62,6 @@ static const char* TAG = "boot";
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static esp_err_t bootloader_main();
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static void print_flash_info(const esp_image_header_t* pfhdr);
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static void update_flash_config(const esp_image_header_t* pfhdr);
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static void vddsdio_configure();
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static void flash_gpio_configure(const esp_image_header_t* pfhdr);
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static void uart_console_configure(void);
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static void wdt_reset_check(void);
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@@ -117,7 +117,7 @@ esp_err_t bootloader_init()
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static esp_err_t bootloader_main()
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{
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vddsdio_configure();
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bootloader_common_vddsdio_configure();
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/* Read and keep flash ID, for further use. */
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g_rom_flashchip.device_id = bootloader_read_flash_id();
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esp_image_header_t fhdr;
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@@ -285,21 +285,6 @@ static void print_flash_info(const esp_image_header_t* phdr)
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#endif
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}
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static void vddsdio_configure()
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{
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#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
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rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
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if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) { // VDDSDIO regulator is enabled @ 1.8V
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cfg.drefh = 3;
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cfg.drefm = 3;
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cfg.drefl = 3;
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cfg.force = 1;
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rtc_vddsdio_set_config(cfg);
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ets_delay_us(10); // wait for regulator to become stable
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}
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#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
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}
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#define FLASH_CLK_IO 6
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#define FLASH_CS_IO 11
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#define FLASH_SPIQ_IO 7
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