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sdm: support sdm on esp32h2

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This commit is contained in:
laokaiyao
2023-01-09 16:31:54 +08:00
parent b1ff550f69
commit 482a26e284
15 changed files with 107 additions and 31 deletions
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6
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
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@@ -35,6 +35,10 @@ config SOC_RTC_MEM_SUPPORTED
bool
default y
config SOC_SDM_SUPPORTED
bool
default y
config SOC_SYSTIMER_SUPPORTED
bool
default y
@@ -531,7 +535,7 @@ config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F80M
config SOC_SDM_CLK_SUPPORT_PLL_F48M
bool
default y

10
components/soc/esp32h2/include/soc/clk_tree_defs.h
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@@ -330,9 +330,13 @@ typedef enum {
* @brief Sigma Delta Modulator clock source
*/
typedef enum {
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the default clock choice */
SDM_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL clock as the source clock */
SDM_CLK_SRC_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M clock as the source clock */
#if CONFIG_IDF_ENV_FPGA
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default clock choice */
#else
SDM_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default clock choice */
#endif
} soc_periph_sdm_clk_src_t;
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////

8
components/soc/esp32h2/include/soc/gpio_ext_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,11 +16,11 @@ extern "C" {
*/
typedef union {
struct {
/** sd0_in : R/W; bitpos: [7:0]; default: 0;
/** duty : R/W; bitpos: [7:0]; default: 0;
* This field is used to configure the duty cycle of sigma delta modulation output.
*/
uint32_t duty:8;
/** sd0_prescale : R/W; bitpos: [15:8]; default: 255;
/** prescale : R/W; bitpos: [15:8]; default: 255;
* This field is used to set a divider value to divide APB clock.
*/
uint32_t prescale:8;
@@ -272,7 +272,7 @@ typedef union {
uint32_t val;
} gpio_ext_version_reg_t;
typedef struct {
typedef struct gpio_sd_dev_t {
volatile gpio_sigmadelta_chn_reg_t channel[4];
uint32_t reserved_010[4];
volatile gpio_sigmadelta_misc_reg_t misc;

5
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -46,7 +46,7 @@
#define SOC_RTC_MEM_SUPPORTED 1
// #define SOC_I2S_SUPPORTED 1 // TODO: IDF-6219
// #define SOC_RMT_SUPPORTED 1 // TODO: IDF-6224
// #define SOC_SDM_SUPPORTED 1 // TODO: IDF-6220
#define SOC_SDM_SUPPORTED 1
// #define SOC_GPSPI_SUPPORTED 1 // TODO: IDF-6264
#define SOC_SYSTIMER_SUPPORTED 1
// #define SOC_SUPPORT_COEXISTENCE 1 // TODO: IDF-6416
@@ -294,11 +294,10 @@
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
// TODO: IDF-6220
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_PLL_F48M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
// TODO: IDF-6245 (Copy from esp32c6, need check)