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esp_common: Add API for IPC to run small pieces of code on the other CPU, in the context of the level 4 interrupt

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This commit is contained in:
Konstantin Kondrashov
2021-08-03 14:35:29 +08:00
committed by Zim Kalinowski
parent a0c548ccd4
commit 4972605b16
51 changed files with 1062 additions and 379 deletions
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4
components/soc/esp32/include/soc/dport_reg.h
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@@ -1156,6 +1156,8 @@
#define DPORT_CPU_INTR_FROM_CPU_1_V 0x1
#define DPORT_CPU_INTR_FROM_CPU_1_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_2_REG DPORT_CPU_INTR_FROM_CPU_2_REG
#define SYSTEM_CPU_INTR_FROM_CPU_2 DPORT_CPU_INTR_FROM_CPU_2
#define DPORT_CPU_INTR_FROM_CPU_2_REG (DR_REG_DPORT_BASE + 0x0E4)
/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */
@@ -1164,6 +1166,8 @@
#define DPORT_CPU_INTR_FROM_CPU_2_V 0x1
#define DPORT_CPU_INTR_FROM_CPU_2_S 0
#define SYSTEM_CPU_INTR_FROM_CPU_3_REG DPORT_CPU_INTR_FROM_CPU_3_REG
#define SYSTEM_CPU_INTR_FROM_CPU_3 DPORT_CPU_INTR_FROM_CPU_3
#define DPORT_CPU_INTR_FROM_CPU_3_REG (DR_REG_DPORT_BASE + 0x0E8)
/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
/*description: */

8
components/soc/esp32/include/soc/soc.h
View File

@@ -307,8 +307,8 @@
#define ETS_GPIO_NMI_SOURCE 23/**< interrupt of GPIO, NMI*/
#define ETS_FROM_CPU_INTR0_SOURCE 24/**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
#define ETS_FROM_CPU_INTR1_SOURCE 25/**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
#define ETS_FROM_CPU_INTR2_SOURCE 26/**< interrupt2 generated from a CPU, level*/ /* Used for IPC_ISR */
#define ETS_FROM_CPU_INTR3_SOURCE 27/**< interrupt3 generated from a CPU, level*/ /* Used for IPC_ISR */
#define ETS_SPI0_INTR_SOURCE 28/**< interrupt of SPI0, level, SPI0 is for Cache Access, do not use this*/
#define ETS_SPI1_INTR_SOURCE 29/**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
#define ETS_SPI2_INTR_SOURCE 30/**< interrupt of SPI2, level*/
@@ -382,7 +382,7 @@
* 25 4 extern level CACHEERR
* 26 5 extern level
* 27 3 extern level Reserved Reserved
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
* 28 4 extern edge IPC_ISR IPC_ISR
* 29 3 software Reserved Reserved
* 30 4 extern edge Reserved Reserved
* 31 5 extern level
@@ -399,7 +399,7 @@
#define ETS_MEMACCESS_ERR_INUM 25
/* backwards compatibility only, use ETS_MEMACCESS_ERR_INUM instead*/
#define ETS_CACHEERR_INUM ETS_MEMACCESS_ERR_INUM
#define ETS_DPORT_INUM 28
#define ETS_IPC_ISR_INUM 28
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
#define ETS_SLC_INUM 1