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feat(gptimer): basic driver support on esp32c5

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This commit is contained in:
morris
2024-02-18 18:12:03 +08:00
parent f68c131e56
commit 49e7228be9
15 changed files with 380 additions and 52 deletions
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16
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -7,6 +7,10 @@ config SOC_UART_SUPPORTED
bool
default y
config SOC_GPTIMER_SUPPORTED
bool
default y
config SOC_EFUSE_KEY_PURPOSE_FIELD
bool
default y
@@ -215,6 +219,18 @@ config SOC_TIMER_GROUP_TIMERS_PER_GROUP
int
default 1
config SOC_TIMER_GROUP_COUNTER_BIT_WIDTH
int
default 54
config SOC_TIMER_GROUP_SUPPORT_XTAL
bool
default y
config SOC_TIMER_GROUP_TOTAL_TIMERS
int
default 2
config SOC_EFUSE_SECURE_BOOT_KEY_DIGESTS
int
default 3

6
components/soc/esp32c5/include/soc/clk_tree_defs.h
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@@ -167,12 +167,12 @@ typedef enum { // TODO: [ESP32C5] IDF-8676 (inherit from C6)
* }
* @endcode
*/
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M, SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL}
#define SOC_GPTIMER_CLKS {SOC_MOD_CLK_PLL_F80M/*, SOC_MOD_CLK_RC_FAST*/, SOC_MOD_CLK_XTAL}
/**
* @brief Type of GPTimer clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6)
typedef enum {
GPTIMER_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
GPTIMER_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
@@ -182,7 +182,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6)
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum { // TODO: [ESP32C5] IDF-8705 (inherit from C6)
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */

9
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -22,7 +22,7 @@
#define SOC_UART_SUPPORTED 1 // TODO: [ESP32C5] IDF-8722
// #define SOC_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710
// #define SOC_AHB_GDMA_SUPPORTED 1 // TODO: [ESP32C5] IDF-8710
// #define SOC_GPTIMER_SUPPORTED 1 // TODO: [ESP32C5] IDF-8705
#define SOC_GPTIMER_SUPPORTED 1
// #define SOC_PCNT_SUPPORTED 1 // TODO: [ESP32C5] IDF-8683
// #define SOC_MCPWM_SUPPORTED 1 // TODO: [ESP32C5] IDF-8709
// #define SOC_TWAI_SUPPORTED 1 // TODO: [ESP32C5] IDF-8691
@@ -426,10 +426,10 @@
/*--------------------------- TIMER GROUP CAPS ---------------------------------------*/
#define SOC_TIMER_GROUPS (2)
#define SOC_TIMER_GROUP_TIMERS_PER_GROUP (1U)
// #define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
// #define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
#define SOC_TIMER_GROUP_COUNTER_BIT_WIDTH (54)
#define SOC_TIMER_GROUP_SUPPORT_XTAL (1)
// #define SOC_TIMER_GROUP_SUPPORT_RC_FAST (1)
// #define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
#define SOC_TIMER_GROUP_TOTAL_TIMERS (2)
// #define SOC_TIMER_SUPPORT_ETM (1)
/*--------------------------- WATCHDOG CAPS ---------------------------------------*/
@@ -516,7 +516,6 @@
/* macro redefine for pass esp_wifi headers md5sum check */
// #define MAC_SUPPORT_PMU_MODEM_STATE SOC_PM_SUPPORT_PMU_MODEM_STATE
// #define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
// #define SOC_PM_CPU_RETENTION_BY_SW (1)

24
components/soc/esp32c5/timer_periph.c Normal file
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@@ -0,0 +1,24 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/timer_periph.h"
const timer_group_signal_conn_t timer_group_periph_signals = {
.groups = {
[0] = {
.module = PERIPH_TIMG0_MODULE,
.timer_irq_id = {
[0] = ETS_TG0_T0_LEVEL_INTR_SOURCE,
}
},
[1] = {
.module = PERIPH_TIMG1_MODULE,
.timer_irq_id = {
[0] = ETS_TG1_T0_LEVEL_INTR_SOURCE,
}
}
}
};