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fix(spi_master): Fix p4 spi clock source support other than XTAL

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This commit is contained in:
wanlei
2024-01-17 17:01:23 +08:00
parent 1903c51d07
commit 4a46d70e9a
8 changed files with 90 additions and 32 deletions
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8
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -987,6 +987,14 @@ config SOC_SPI_SUPPORT_CLK_XTAL
bool
default y
config SOC_SPI_SUPPORT_CLK_RC_FAST
bool
default y
config SOC_SPI_SUPPORT_CLK_SPLL
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT
bool
default y

12
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -403,14 +403,10 @@ typedef enum {
* @brief Type of SPI clock source.
*/
typedef enum {
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
#if SOC_CLK_TREE_SUPPORTED
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST,
SPI_CLK_SRC_SPLL_480 = SOC_MOD_CLK_SPLL,
SPI_CLK_SRC_DEFAULT = SPI_CLK_SRC_SPLL_480, /*!< Select SPLL_480M as SPI source clock */
#else
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
#endif
SPI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as SPI source clock */
SPI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST_20M as SPI source clock */
SPI_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SPLL as SPI source clock */
SPI_CLK_SRC_DEFAULT = SOC_MOD_CLK_SPLL, /*!< Select SPLL as SPI source clock */
} soc_periph_spi_clk_src_t;
/////////////////////////////////////////////////PSRAM////////////////////////////////////////////////////////////////////

8
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -425,10 +425,8 @@
#define SOC_SPI_SUPPORT_CD_SIG 1
#define SOC_SPI_SUPPORT_OCT 1
#define SOC_SPI_SUPPORT_CLK_XTAL 1
// #define SOC_SPI_SUPPORT_CLK_RC_FAST 1 //bellow clks are waiting for clock tree
// #define SOC_SPI_SUPPORT_CLK_SPLL_F480M 1 //super pll
// #define SOC_SPI_SUPPORT_CLK_SDIO 1 //sdio pll
// #define SOC_SPI_SUPPORT_CLK_APLL 1 //audio pll
#define SOC_SPI_SUPPORT_CLK_RC_FAST 1
#define SOC_SPI_SUPPORT_CLK_SPLL 1
// Peripheral supports DIO, DOUT, QIO, or QOUT
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,