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fix(ledc): clear ledc_mem_force_pd when LEDC peripheral is in use
And enable target test for C5 and P4
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2019-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -46,7 +46,8 @@ extern "C" {
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*
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* @param enable Enable/Disable
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*/
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static inline void ledc_ll_enable_bus_clock(bool enable) {
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static inline void ledc_ll_enable_bus_clock(bool enable)
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{
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if (enable) {
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_LEDC_CLK_EN);
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} else {
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@@ -61,7 +62,8 @@ static inline void ledc_ll_enable_bus_clock(bool enable) {
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/**
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* @brief Reset whole peripheral register to init value defined by HW design
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*/
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static inline void ledc_ll_enable_reset_reg(bool enable) {
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static inline void ledc_ll_enable_reset_reg(bool enable)
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{
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if (enable) {
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_LEDC_RST);
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} else {
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@@ -73,6 +75,14 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define ledc_ll_enable_reset_reg(...) (void)__DECLARE_RCC_ATOMIC_ENV; ledc_ll_enable_reset_reg(__VA_ARGS__)
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/**
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* @brief Enable the power for LEDC memory block
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*/
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static inline void ledc_ll_enable_mem_power(bool enable)
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{
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// No LEDC mem block on ESP32
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}
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/**
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* @brief Enable LEDC function clock
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*
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@@ -81,7 +91,8 @@ static inline void ledc_ll_enable_reset_reg(bool enable) {
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*
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* @return None
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*/
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static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en) {
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static inline void ledc_ll_enable_clock(ledc_dev_t *hw, bool en)
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{
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//resolve for compatibility
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}
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