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fix(ledc): clear ledc_mem_force_pd when LEDC peripheral is in use

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And enable target test for C5 and P4
This commit is contained in:
Song Ruo Jing
2024-07-01 19:43:40 +08:00
parent f978dd0af9
commit 4cd74f51db
13 changed files with 144 additions and 49 deletions
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18
components/hal/esp32c6/include/hal/ledc_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -38,17 +38,27 @@ extern "C" {
*
* @param enable Enable/Disable
*/
static inline void ledc_ll_enable_bus_clock(bool enable) {
static inline void ledc_ll_enable_bus_clock(bool enable)
{
PCR.ledc_conf.ledc_clk_en = enable;
}
/**
* @brief Reset whole peripheral register to init value defined by HW design
*/
static inline void ledc_ll_enable_reset_reg(bool enable) {
static inline void ledc_ll_enable_reset_reg(bool enable)
{
PCR.ledc_conf.ledc_rst_en = enable;
}
/**
* @brief Enable the power for LEDC memory block
*/
static inline void ledc_ll_enable_mem_power(bool enable)
{
// No register to control the power for LEDC memory block on C6
}
/**
* @brief Enable LEDC function clock
*
@@ -539,7 +549,7 @@ static inline void ledc_ll_get_fade_param(ledc_dev_t *hw, ledc_mode_t speed_mode
static inline void ledc_ll_get_fade_param_range(ledc_dev_t *hw, ledc_mode_t speed_mode, ledc_channel_t channel_num, uint8_t range, uint32_t *dir, uint32_t *cycle, uint32_t *scale, uint32_t *step)
{
// On ESP32C6/H2, gamma ram read/write has the APB and LEDC clock domain sync issue
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure syncronization
// To make sure the parameter read is from the correct gamma ram addr, add a delay in between to ensure synchronization
ledc_ll_set_duty_range_rd_addr(hw, speed_mode, channel_num, range);
esp_rom_delay_us(5);
ledc_ll_get_fade_param(hw, speed_mode, channel_num, dir, cycle, scale, step);