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fix(system): update reset reasons for P4 and C5

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This commit is contained in:
Marius Vikhammer
2024-02-08 18:17:15 +08:00
parent c0a2043562
commit 4ce4af61ad
7 changed files with 111 additions and 89 deletions
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76
components/esp_rom/include/esp32c5/rom/rtc.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -75,46 +75,48 @@ typedef enum {
} SLEEP_MODE;
typedef enum {
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Vbat power on reset*/
RTC_SW_SYS_RESET = 3, /**<3, Software reset digital core (hp system)*/
DEEPSLEEP_RESET = 5, /**<5, Deep Sleep reset digital core (hp system)*/
SDIO_RESET = 6, /**<6, Reset by SLC module, reset digital core (hp system)*/
TG0WDT_SYS_RESET = 7, /**<7, Timer Group0 Watch dog reset digital core (hp system)*/
TG1WDT_SYS_RESET = 8, /**<8, Timer Group1 Watch dog reset digital core (hp system)*/
RTCWDT_SYS_RESET = 9, /**<9, RTC Watch dog Reset digital core (hp system)*/
TG0WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
RTC_SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTCWDT_CPU_RESET = 13, /**<13, RTC Watch dog Reset CPU*/
RTCWDT_BROWN_OUT_RESET = 15, /**<15, Reset when the vdd voltage is not stable*/
RTCWDT_RTC_RESET = 16, /**<16, RTC Watch dog reset digital core and rtc module*/
TG1WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
SUPER_WDT_RESET = 18, /**<18, super watchdog reset digital core and rtc module*/
EFUSE_RESET = 20, /**<20, efuse reset digital core (hp system)*/
USB_UART_CHIP_RESET = 21, /**<21, usb uart reset digital core (hp system)*/
USB_JTAG_CHIP_RESET = 22, /**<22, usb jtag reset digital core (hp system)*/
JTAG_RESET = 24, /**<24, jtag reset CPU*/
NO_MEAN = 0,
POWERON_RESET = 1, /**<1, Power on reset*/
RTC_SW_HPSYS_RESET = 3, /**<3, Software reset hp system*/
SLEEP_WAKEUP = 5, /**<5, Deep Sleep reset hp system*/
TG0_WDT_HPSYS_RESET = 7, /**<7, Timer Group0 Watch dog reset hp system*/
TG1_WDT_HPSYS_RESET = 8, /**<8, Timer Group1 Watch dog reset hp system*/
RTC_WDT_HPSYS_RESET = 9, /**<9, RTC Watch dog Reset hp system*/
TG0_WDT_CPU_RESET = 11, /**<11, Time Group0 reset CPU*/
SW_CPU_RESET = 12, /**<12, Software reset CPU*/
RTC_WDT_CPU_RESET = 13, /**<13, RTC Watch dog reset CPU*/
RTC_BOD_SYS_RESET = 15, /**<15, System reset when the vdd voltage is not stable*/
RTC_WDT_SYS_RESET = 16, /**<16, RTC Watch dog reset system*/
TG1_WDT_CPU_RESET = 17, /**<17, Time Group1 reset CPU*/
RTC_SWDT_SYS_RESET = 18, /**<18, super watchdog reset system*/
EFUSE_HPSYS_RESET = 20, /**<20, efuse reset hp system*/
USB_UART_HPSYS_RESET = 21, /**<21, usb uart reset hp system*/
USB_JTAG_HPSYS_RESET = 22, /**<22, usb jtag reset hp system*/
JTAG_CPU_RESET = 24, /**<24, jtag reset CPU*/
RTC_PWR_GLITCH_RESET = 25, /**<25, RTC power glitch reset system*/
CPU_LOCKUP_RESET = 26, /**<26, cpu lockup reset*/
} RESET_REASON;
// Check if the reset reason defined in ROM is compatible with soc/reset_reasons.h
ESP_STATIC_ASSERT((soc_reset_reason_t)POWERON_RESET == RESET_REASON_CHIP_POWER_ON, "POWERON_RESET != RESET_REASON_CHIP_POWER_ON");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_SYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_SYS_RESET != RESET_REASON_CORE_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)DEEPSLEEP_RESET == RESET_REASON_CORE_DEEP_SLEEP, "DEEPSLEEP_RESET != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)SDIO_RESET == RESET_REASON_CORE_SDIO, "SDIO_RESET != RESET_REASON_CORE_SDIO");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_SYS_RESET == RESET_REASON_CORE_MWDT0, "TG0WDT_SYS_RESET != RESET_REASON_CORE_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_SYS_RESET == RESET_REASON_CORE_MWDT1, "TG1WDT_SYS_RESET != RESET_REASON_CORE_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_SYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTCWDT_SYS_RESET != RESET_REASON_CORE_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_CPU_RESET == RESET_REASON_CPU0_SW, "RTC_SW_CPU_RESET != RESET_REASON_CPU0_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTCWDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_BROWN_OUT_RESET == RESET_REASON_SYS_BROWN_OUT, "RTCWDT_BROWN_OUT_RESET != RESET_REASON_SYS_BROWN_OUT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTCWDT_RTC_RESET == RESET_REASON_SYS_RTC_WDT, "RTCWDT_RTC_RESET != RESET_REASON_SYS_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)SUPER_WDT_RESET == RESET_REASON_SYS_SUPER_WDT, "SUPER_WDT_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_CHIP_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_CHIP_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_CHIP_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_CHIP_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_RESET == RESET_REASON_CPU0_JTAG, "JTAG_RESET != RESET_REASON_CPU0_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SW_HPSYS_RESET == RESET_REASON_CORE_SW, "RTC_SW_HPSYS_RESET != RESET_REASON_CORE_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)SLEEP_WAKEUP == RESET_REASON_CORE_DEEP_SLEEP, "SLEEP_WAKEUP != RESET_REASON_CORE_DEEP_SLEEP");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0_WDT_HPSYS_RESET == RESET_REASON_CORE_MWDT0, "TG0_WDT_HPSYS_RESET != RESET_REASON_CORE_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1_WDT_HPSYS_RESET == RESET_REASON_CORE_MWDT1, "TG1_WDT_HPSYS_RESET != RESET_REASON_CORE_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_HPSYS_RESET == RESET_REASON_CORE_RTC_WDT, "RTC_WDT_HPSYS_RESET != RESET_REASON_CORE_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG0_WDT_CPU_RESET == RESET_REASON_CPU0_MWDT0, "TG0_WDT_CPU_RESET != RESET_REASON_CPU0_MWDT0");
ESP_STATIC_ASSERT((soc_reset_reason_t)SW_CPU_RESET == RESET_REASON_CPU0_SW, "SW_CPU_RESET != RESET_REASON_CPU0_SW");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_CPU_RESET == RESET_REASON_CPU0_RTC_WDT, "RTC_WDT_CPU_RESET != RESET_REASON_CPU0_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_BOD_SYS_RESET == RESET_REASON_SYS_BROWN_OUT, "RTC_BOD_SYS_RESET != RESET_REASON_SYS_BROWN_OUT");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_WDT_SYS_RESET == RESET_REASON_SYS_RTC_WDT, "RTC_WDT_SYS_RESET != RESET_REASON_SYS_RTC_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)TG1_WDT_CPU_RESET == RESET_REASON_CPU0_MWDT1, "TG1_WDT_CPU_RESET != RESET_REASON_CPU0_MWDT1");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_SWDT_SYS_RESET == RESET_REASON_SYS_SUPER_WDT, "RTC_SWDT_SYS_RESET != RESET_REASON_SYS_SUPER_WDT");
ESP_STATIC_ASSERT((soc_reset_reason_t)EFUSE_HPSYS_RESET == RESET_REASON_CORE_EFUSE_CRC, "EFUSE_HPSYS_RESET != RESET_REASON_CORE_EFUSE_CRC");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_UART_HPSYS_RESET == RESET_REASON_CORE_USB_UART, "USB_UART_HPSYS_RESET != RESET_REASON_CORE_USB_UART");
ESP_STATIC_ASSERT((soc_reset_reason_t)USB_JTAG_HPSYS_RESET == RESET_REASON_CORE_USB_JTAG, "USB_JTAG_HPSYS_RESET != RESET_REASON_CORE_USB_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)JTAG_CPU_RESET == RESET_REASON_CPU0_JTAG, "JTAG_CPU_RESET != RESET_REASON_CPU0_JTAG");
ESP_STATIC_ASSERT((soc_reset_reason_t)RTC_PWR_GLITCH_RESET == RESET_REASON_CORE_PWR_GLITCH, "RTC_PWR_GLITCH_RESET != RESET_REASON_CORE_PWR_GLITCH");
ESP_STATIC_ASSERT((soc_reset_reason_t)CPU_LOCKUP_RESET == RESET_REASON_CPU0_LOCKUP, "CPU_LOCKUP_RESET != RESET_REASON_CPU0_LOCKUP");
typedef enum {
NO_SLEEP = 0,