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Merge branch 'change/bu_lp_i2c_c5' into 'master'
change(ulp): bring up lp i2c on esp32c5 Closes IDF-8634 See merge request espressif/esp-idf!32142
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@@ -167,6 +167,10 @@ config SOC_LP_PERIPHERALS_SUPPORTED
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bool
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default y
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config SOC_LP_I2C_SUPPORTED
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bool
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default y
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config SOC_ULP_LP_UART_SUPPORTED
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bool
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default y
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@@ -509,7 +513,7 @@ config SOC_DEDIC_PERIPH_ALWAYS_ENABLE
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config SOC_I2C_NUM
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int
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default 1
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default 2
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config SOC_HP_I2C_NUM
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int
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@@ -559,6 +563,14 @@ config SOC_I2C_SLAVE_SUPPORT_SLAVE_UNMATCH
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bool
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default y
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config SOC_LP_I2C_NUM
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int
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default 1
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config SOC_LP_I2C_FIFO_LEN
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int
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default 16
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config SOC_I2S_NUM
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int
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default 1
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@@ -340,15 +340,15 @@ typedef enum { // TODO: [ESP32C5] IDF-8694, IDF-8696 (inherit from C6)
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/**
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* @brief Array initializer for all supported clock sources of LP_I2C
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*/
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#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RTC_FAST, SOC_MOD_CLK_XTAL_D2}
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#define SOC_LP_I2C_CLKS {SOC_MOD_CLK_RC_FAST, SOC_MOD_CLK_XTAL_D2}
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/**
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* @brief Type of LP_I2C clock source.
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*/
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typedef enum { // TODO: [ESP32C5] IDF-8695 (inherit from C6)
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LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock is RTC_FAST */
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LP_I2C_SCLK_LP_FAST = SOC_MOD_CLK_RC_FAST, /*!< LP_I2C source clock is RC_FAST */
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LP_I2C_SCLK_XTAL_D2 = SOC_MOD_CLK_XTAL_D2, /*!< LP_I2C source clock is XTAL_D2 */
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LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RTC_FAST, /*!< LP_I2C source clock default choice is RTC_FAST */
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LP_I2C_SCLK_DEFAULT = SOC_MOD_CLK_RC_FAST, /*!< LP_I2C source clock default choice is RC_FAST */
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} soc_periph_lp_i2c_clk_src_t;
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/////////////////////////////////////////////////SPI////////////////////////////////////////////////////////////////////
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@@ -1103,6 +1103,7 @@ typedef struct {
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} i2c_dev_t;
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extern i2c_dev_t I2C0;
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extern i2c_dev_t LP_I2C;
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#ifndef __cplusplus
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_Static_assert(sizeof(i2c_dev_t) == 0x200, "Invalid size of i2c_dev_t structure");
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@@ -63,7 +63,7 @@
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#define SOC_LP_TIMER_SUPPORTED 1
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// #define SOC_LP_AON_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
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#define SOC_LP_PERIPHERALS_SUPPORTED 1
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// #define SOC_LP_I2C_SUPPORTED 1 // TODO: [ESP32C5] IDF-8634
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#define SOC_LP_I2C_SUPPORTED 1
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#define SOC_ULP_LP_UART_SUPPORTED 1
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#define SOC_CLK_TREE_SUPPORTED 1
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// #define SOC_ASSIST_DEBUG_SUPPORTED 1 // TODO: [ESP32C5] IDF-8663
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@@ -243,8 +243,7 @@
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#define SOC_DEDIC_PERIPH_ALWAYS_ENABLE (1) /*!< The dedicated GPIO (a.k.a. fast GPIO) is featured by some customized CPU instructions, which is always enabled */
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/*-------------------------- I2C CAPS ----------------------------------------*/
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// ESP32-C5 has 1 I2C
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#define SOC_I2C_NUM (1U)
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#define SOC_I2C_NUM (2U)
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#define SOC_HP_I2C_NUM (1U)
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#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
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@@ -264,9 +263,9 @@
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/*-------------------------- LP_I2C CAPS -------------------------------------*/
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// ESP32-C5 has 1 LP_I2C
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// #define SOC_LP_I2C_NUM (1U)
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#define SOC_LP_I2C_NUM (1U)
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// #define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
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#define SOC_LP_I2C_FIFO_LEN (16) /*!< LP_I2C hardware FIFO depth */
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/*-------------------------- I2S CAPS ----------------------------------------*/
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#define SOC_I2S_NUM (1U)
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