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esp32 phy_init: Move DPORT Wifi clock masks to macro values

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Amended fix for c642079 !534
This commit is contained in:
Angus Gratton
2017-03-01 12:02:04 +11:00
parent 98f8594151
commit 4d67a2ba8b
3 changed files with 24 additions and 3 deletions
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16
components/esp32/include/soc/dport_reg.h
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@@ -1035,6 +1035,22 @@
#define DPORT_WIFI_CLK_EN_V 0xFFFFFFFF
#define DPORT_WIFI_CLK_EN_S 0
/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15 */
#define DPORT_WIFI_CLK_WIFI_EN 0x000007cf
#define DPORT_WIFI_CLK_WIFI_EN_M ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
#define DPORT_WIFI_CLK_WIFI_EN_V 0x1FF
#define DPORT_WIFI_CLK_WIFI_EN_S 0
/* Mask for all Bluetooth clock bits - 11, 16, 17 */
#define DPORT_WIFI_CLK_BT_EN 0x61
#define DPORT_WIFI_CLK_BT_EN_M ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S))
#define DPORT_WIFI_CLK_BT_EN_V 0x61
#define DPORT_WIFI_CLK_BT_EN_S 11
/* Remaining single bit clock masks */
#define DPORT_WIFI_CLK_SDIOSLAVE_EN BIT(4)
#define DPORT_WIFI_CLK_SDIO_HOST_EN BIT(13)
#define DPORT_WIFI_CLK_EMAC_EN BIT(14)
#define DPORT_WIFI_CLK_RNG_EN BIT(15)
#define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0)
/* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
/*description: */