mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-09 12:35:28 +00:00
adc: support adc dma driver on all chips
This commit is contained in:
Armando
committed by
Armando (Dou Yiwen)
Armando (Dou Yiwen)
parent
5ddce053ea
commit
4dc0d6b2fe
@@ -11,229 +11,24 @@
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#include "esp_log.h"
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#include "sys/lock.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/xtensa_api.h"
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#include "freertos/semphr.h"
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#include "freertos/timers.h"
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#include "esp_pm.h"
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#include "esp_intr_alloc.h"
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#include "esp_private/periph_ctrl.h"
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#include "driver/rtc_io.h"
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#include "driver/rtc_cntl.h"
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#include "driver/gpio.h"
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#include "driver/adc.h"
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#include "esp_efuse_rtc_table.h"
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#include "hal/adc_types.h"
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#include "hal/adc_hal.h"
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#define ADC_CHECK_RET(fun_ret) ({ \
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if (fun_ret != ESP_OK) { \
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ESP_LOGE(ADC_TAG,"%s:%d\n",__FUNCTION__,__LINE__); \
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return ESP_FAIL; \
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} \
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})
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static const char *ADC_TAG = "ADC";
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#define ADC_CHECK(a, str, ret_val) ({ \
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if (!(a)) { \
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ESP_LOGE(ADC_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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} \
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})
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#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
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#define ADC_CHANNEL_CHECK(periph, channel) ADC_CHECK(channel < SOC_ADC_CHANNEL_NUM(periph), "ADC"#periph" channel error", ESP_ERR_INVALID_ARG)
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#include "hal/adc_ll.h"
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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#define ADC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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#define ADC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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#ifdef CONFIG_PM_ENABLE
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static esp_pm_lock_handle_t s_adc_digi_arbiter_lock = NULL;
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#endif //CONFIG_PM_ENABLE
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esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten);
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/*---------------------------------------------------------------
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Digital controller setting
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---------------------------------------------------------------*/
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esp_err_t adc_digi_init(void)
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{
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adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
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ADC_ENTER_CRITICAL();
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adc_hal_init();
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adc_hal_arbiter_config(&config);
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ADC_EXIT_CRITICAL();
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adc_hal_calibration_init(ADC_NUM_1);
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adc_hal_calibration_init(ADC_NUM_2);
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return ESP_OK;
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}
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esp_err_t adc_digi_deinit(void)
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{
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#ifdef CONFIG_PM_ENABLE
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if (s_adc_digi_arbiter_lock) {
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esp_pm_lock_delete(s_adc_digi_arbiter_lock);
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s_adc_digi_arbiter_lock = NULL;
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}
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#endif
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adc_power_release();
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ADC_ENTER_CRITICAL();
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adc_hal_digi_deinit();
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
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{
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#ifdef CONFIG_PM_ENABLE
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esp_err_t err;
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if (s_adc_digi_arbiter_lock == NULL) {
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if (config->dig_clk.use_apll) {
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err = esp_pm_lock_create(ESP_PM_NO_LIGHT_SLEEP, 0, "adc_dma", &s_adc_digi_arbiter_lock);
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} else {
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err = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc_dma", &s_adc_digi_arbiter_lock);
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}
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if (err != ESP_OK) {
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s_adc_digi_arbiter_lock = NULL;
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ESP_LOGE(ADC_TAG, "ADC-DMA pm lock error");
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return err;
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}
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}
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#endif //CONFIG_PM_ENABLE
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if (config->conv_mode & ADC_CONV_SINGLE_UNIT_1) {
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for (int i = 0; i < config->adc1_pattern_len; i++) {
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adc_cal_offset(ADC_NUM_1, config->adc1_pattern[i].channel, config->adc1_pattern[i].atten);
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}
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}
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if (config->conv_mode & ADC_CONV_SINGLE_UNIT_2) {
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for (int i = 0; i < config->adc2_pattern_len; i++) {
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adc_cal_offset(ADC_NUM_2, config->adc2_pattern[i].channel, config->adc2_pattern[i].atten);
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}
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}
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/* If enable digtal controller, adc xpd should always on. */
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adc_power_acquire();
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ADC_ENTER_CRITICAL();
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adc_hal_digi_controller_config(config);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc_arbiter_config(adc_unit_t adc_unit, adc_arbiter_t *config)
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{
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if (adc_unit & ADC_UNIT_1) {
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return ESP_ERR_NOT_SUPPORTED;
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}
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ADC_ENTER_CRITICAL();
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adc_hal_arbiter_config(config);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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/**
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* @brief Set ADC module controller.
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* There are five SAR ADC controllers:
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* Two digital controller: Continuous conversion mode (DMA). High performance with multiple channel scan modes;
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* Two RTC controller: Single conversion modes (Polling). For low power purpose working during deep sleep;
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* the other is dedicated for Power detect (PWDET / PKDET), Only support ADC2.
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* Config monitor of adc digital controller.
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*
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* @note Only ADC2 support arbiter to switch controllers automatically. Access to the ADC is based on the priority of the controller.
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* @note For ADC1, Controller access is mutually exclusive.
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*
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* @param adc_unit ADC unit.
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* @param ctrl ADC controller, Refer to `adc_ll_controller_t`.
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*
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* @return
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* - ESP_OK Success
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* @note The monitor will monitor all the enabled channel data of the each ADC unit at the same time.
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* @param adc_n ADC unit.
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* @param config Refer to ``adc_digi_monitor_t``.
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*/
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esp_err_t adc_set_controller(adc_unit_t adc_unit, adc_ll_controller_t ctrl)
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static void adc_digi_monitor_config(adc_ll_num_t adc_n, adc_digi_monitor_t *config)
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{
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adc_arbiter_t config = {0};
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adc_arbiter_t cfg = ADC_ARBITER_CONFIG_DEFAULT();
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if (adc_unit & ADC_UNIT_1) {
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adc_hal_set_controller(ADC_NUM_1, ctrl);
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}
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if (adc_unit & ADC_UNIT_2) {
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adc_hal_set_controller(ADC_NUM_2, ctrl);
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switch (ctrl) {
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case ADC2_CTRL_FORCE_PWDET:
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config.pwdet_pri = 2;
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config.mode = ADC_ARB_MODE_SHIELD;
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adc_hal_arbiter_config(&config);
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adc_hal_set_controller(ADC_NUM_2, ADC2_CTRL_PWDET);
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break;
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case ADC2_CTRL_FORCE_RTC:
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config.rtc_pri = 2;
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config.mode = ADC_ARB_MODE_SHIELD;
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adc_hal_arbiter_config(&config);
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adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_RTC);
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break;
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case ADC2_CTRL_FORCE_ULP:
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config.rtc_pri = 2;
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config.mode = ADC_ARB_MODE_SHIELD;
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adc_hal_arbiter_config(&config);
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adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_ULP);
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break;
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case ADC2_CTRL_FORCE_DIG:
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config.dig_pri = 2;
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config.mode = ADC_ARB_MODE_SHIELD;
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adc_hal_arbiter_config(&config);
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adc_hal_set_controller(ADC_NUM_2, ADC_CTRL_DIG);
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break;
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default:
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adc_hal_arbiter_config(&cfg);
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break;
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}
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}
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return ESP_OK;
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}
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esp_err_t adc_digi_start(void)
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{
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#ifdef CONFIG_PM_ENABLE
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ADC_CHECK((s_adc_digi_arbiter_lock), "Should start after call `adc_digi_controller_config`", ESP_FAIL);
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esp_pm_lock_acquire(s_adc_digi_arbiter_lock);
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#endif
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ADC_ENTER_CRITICAL();
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adc_hal_digi_enable();
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc_digi_stop(void)
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{
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#ifdef CONFIG_PM_ENABLE
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if (s_adc_digi_arbiter_lock) {
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esp_pm_lock_release(s_adc_digi_arbiter_lock);
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}
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#endif
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ADC_ENTER_CRITICAL();
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adc_hal_digi_disable();
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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/**
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* @brief Reset FSM of adc digital controller.
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*
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* @return
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* - ESP_OK Success
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*/
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esp_err_t adc_digi_reset(void)
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{
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ADC_ENTER_CRITICAL();
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adc_hal_digi_reset();
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adc_hal_digi_clear_pattern_table(ADC_NUM_1);
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adc_hal_digi_clear_pattern_table(ADC_NUM_2);
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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adc_ll_digi_monitor_set_mode(adc_n, config->mode);
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adc_ll_digi_monitor_set_thres(adc_n, config->threshold);
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}
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/*************************************/
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@@ -244,9 +39,9 @@ esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx)
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{
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ADC_ENTER_CRITICAL();
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if (idx == ADC_DIGI_FILTER_IDX0) {
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adc_hal_digi_filter_reset(ADC_NUM_1);
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adc_ll_digi_filter_reset(ADC_NUM_1);
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} else if (idx == ADC_DIGI_FILTER_IDX1) {
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adc_hal_digi_filter_reset(ADC_NUM_2);
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adc_ll_digi_filter_reset(ADC_NUM_2);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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@@ -256,9 +51,9 @@ esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_
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{
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ADC_ENTER_CRITICAL();
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if (idx == ADC_DIGI_FILTER_IDX0) {
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adc_hal_digi_filter_set_factor(ADC_NUM_1, config->mode);
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adc_ll_digi_filter_set_factor(ADC_NUM_1, config->mode);
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} else if (idx == ADC_DIGI_FILTER_IDX1) {
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adc_hal_digi_filter_set_factor(ADC_NUM_2, config->mode);
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adc_ll_digi_filter_set_factor(ADC_NUM_2, config->mode);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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@@ -270,11 +65,11 @@ esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_
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if (idx == ADC_DIGI_FILTER_IDX0) {
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config->adc_unit = ADC_UNIT_1;
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config->channel = ADC_CHANNEL_MAX;
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adc_hal_digi_filter_get_factor(ADC_NUM_1, &config->mode);
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adc_ll_digi_filter_get_factor(ADC_NUM_1, &config->mode);
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} else if (idx == ADC_DIGI_FILTER_IDX1) {
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config->adc_unit = ADC_UNIT_2;
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config->channel = ADC_CHANNEL_MAX;
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adc_hal_digi_filter_get_factor(ADC_NUM_2, &config->mode);
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adc_ll_digi_filter_get_factor(ADC_NUM_2, &config->mode);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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@@ -284,9 +79,9 @@ esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable)
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{
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ADC_ENTER_CRITICAL();
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if (idx == ADC_DIGI_FILTER_IDX0) {
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adc_hal_digi_filter_enable(ADC_NUM_1, enable);
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adc_ll_digi_filter_enable(ADC_NUM_1, enable);
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} else if (idx == ADC_DIGI_FILTER_IDX1) {
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adc_hal_digi_filter_enable(ADC_NUM_2, enable);
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adc_ll_digi_filter_enable(ADC_NUM_2, enable);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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@@ -303,9 +98,9 @@ esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable)
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int adc_digi_filter_read_data(adc_digi_filter_idx_t idx)
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{
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if (idx == ADC_DIGI_FILTER_IDX0) {
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return adc_hal_digi_filter_read_data(ADC_NUM_1);
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return adc_ll_digi_filter_read_data(ADC_NUM_1);
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} else if (idx == ADC_DIGI_FILTER_IDX1) {
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return adc_hal_digi_filter_read_data(ADC_NUM_2);
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return adc_ll_digi_filter_read_data(ADC_NUM_2);
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} else {
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return -1;
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}
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@@ -319,9 +114,9 @@ esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monit
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{
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ADC_ENTER_CRITICAL();
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if (idx == ADC_DIGI_MONITOR_IDX0) {
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adc_hal_digi_monitor_config(ADC_NUM_1, config);
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adc_digi_monitor_config(ADC_NUM_1, config);
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} else if (idx == ADC_DIGI_MONITOR_IDX1) {
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adc_hal_digi_monitor_config(ADC_NUM_2, config);
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adc_digi_monitor_config(ADC_NUM_2, config);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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@@ -331,148 +126,10 @@ esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable)
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{
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ADC_ENTER_CRITICAL();
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if (idx == ADC_DIGI_MONITOR_IDX0) {
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adc_hal_digi_monitor_enable(ADC_NUM_1, enable);
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adc_ll_digi_monitor_enable(ADC_NUM_1, enable);
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} else if (idx == ADC_DIGI_MONITOR_IDX1) {
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adc_hal_digi_monitor_enable(ADC_NUM_2, enable);
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adc_ll_digi_monitor_enable(ADC_NUM_2, enable);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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/**************************************/
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/* Digital controller intr setting */
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/**************************************/
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esp_err_t adc_digi_intr_enable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
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{
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ADC_ENTER_CRITICAL();
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if (adc_unit & ADC_UNIT_1) {
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adc_hal_digi_intr_enable(ADC_NUM_1, intr_mask);
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}
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if (adc_unit & ADC_UNIT_2) {
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adc_hal_digi_intr_enable(ADC_NUM_2, intr_mask);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc_digi_intr_disable(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
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{
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ADC_ENTER_CRITICAL();
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if (adc_unit & ADC_UNIT_1) {
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adc_hal_digi_intr_disable(ADC_NUM_1, intr_mask);
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}
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if (adc_unit & ADC_UNIT_2) {
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adc_hal_digi_intr_disable(ADC_NUM_2, intr_mask);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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esp_err_t adc_digi_intr_clear(adc_unit_t adc_unit, adc_digi_intr_t intr_mask)
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{
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ADC_ENTER_CRITICAL();
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if (adc_unit & ADC_UNIT_1) {
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adc_hal_digi_intr_clear(ADC_NUM_1, intr_mask);
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}
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if (adc_unit & ADC_UNIT_2) {
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adc_hal_digi_intr_clear(ADC_NUM_2, intr_mask);
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}
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ADC_EXIT_CRITICAL();
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return ESP_OK;
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}
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uint32_t adc_digi_intr_get_status(adc_unit_t adc_unit)
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{
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uint32_t ret = 0;
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ADC_ENTER_CRITICAL();
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if (adc_unit & ADC_UNIT_1) {
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ret = adc_hal_digi_get_intr_status(ADC_NUM_1);
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}
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if (adc_unit & ADC_UNIT_2) {
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ret = adc_hal_digi_get_intr_status(ADC_NUM_2);
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}
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ADC_EXIT_CRITICAL();
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return ret;
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}
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static uint8_t s_isr_registered = 0;
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static intr_handle_t s_adc_isr_handle = NULL;
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esp_err_t adc_digi_isr_register(void (*fn)(void *), void *arg, int intr_alloc_flags)
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{
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ADC_CHECK((fn != NULL), "Parameter error", ESP_ERR_INVALID_ARG);
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ADC_CHECK(s_isr_registered == 0, "ADC ISR have installed, can not install again", ESP_FAIL);
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esp_err_t ret = esp_intr_alloc(ETS_APB_ADC_INTR_SOURCE, intr_alloc_flags, fn, arg, &s_adc_isr_handle);
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if (ret == ESP_OK) {
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s_isr_registered = 1;
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}
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return ret;
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}
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esp_err_t adc_digi_isr_deregister(void)
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||||
{
|
||||
esp_err_t ret = ESP_FAIL;
|
||||
if (s_isr_registered) {
|
||||
ret = esp_intr_free(s_adc_isr_handle);
|
||||
if (ret == ESP_OK) {
|
||||
s_isr_registered = 0;
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
RTC controller setting
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
/*---------------------------------------------------------------
|
||||
Calibration
|
||||
---------------------------------------------------------------*/
|
||||
|
||||
static uint16_t s_adc_cali_param[ADC_NUM_MAX][ADC_ATTEN_MAX] = { {0}, {0} };
|
||||
|
||||
//NOTE: according to calibration version, different types of lock may be taken during the process:
|
||||
// 1. Semaphore when reading efuse
|
||||
// 2. Spinlock when actually doing ADC calibration
|
||||
//This function shoudn't be called inside critical section or ISR
|
||||
uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
|
||||
{
|
||||
#ifdef CONFIG_IDF_ENV_FPGA
|
||||
return 0;
|
||||
#endif
|
||||
|
||||
if (s_adc_cali_param[adc_n][atten]) {
|
||||
ESP_LOGV(ADC_TAG, "Use calibrated val ADC%d atten=%d: %04X", adc_n, atten, s_adc_cali_param[adc_n][atten]);
|
||||
return (uint32_t)s_adc_cali_param[adc_n][atten];
|
||||
}
|
||||
|
||||
uint32_t dout = 0;
|
||||
// check if we can fetch the values from eFuse.
|
||||
int version = esp_efuse_rtc_table_read_calib_version();
|
||||
if (version == 2) {
|
||||
int tag = esp_efuse_rtc_table_get_tag(version, adc_n + 1, atten, RTCCALIB_V2_PARAM_VINIT);
|
||||
dout = esp_efuse_rtc_table_get_parsed_efuse_value(tag, false);
|
||||
} else {
|
||||
adc_power_acquire();
|
||||
ADC_ENTER_CRITICAL();
|
||||
const bool internal_gnd = true;
|
||||
dout = adc_hal_self_calibration(adc_n, channel, atten, internal_gnd);
|
||||
ADC_EXIT_CRITICAL();
|
||||
adc_power_release();
|
||||
}
|
||||
ESP_LOGD(ADC_TAG, "Calib(V%d) ADC%d atten=%d: %04X", version, adc_n, atten, dout);
|
||||
s_adc_cali_param[adc_n][atten] = (uint16_t)dout;
|
||||
return dout;
|
||||
}
|
||||
|
||||
esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
|
||||
{
|
||||
adc_hal_calibration_init(adc_n);
|
||||
uint32_t cal_val = adc_get_calibration_offset(adc_n, channel, atten);
|
||||
ADC_ENTER_CRITICAL();
|
||||
adc_hal_set_calibration_param(adc_n, cal_val);
|
||||
ADC_EXIT_CRITICAL();
|
||||
return ESP_OK;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user