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adc: support adc dma driver on all chips
This commit is contained in:

committed by
Armando (Dou Yiwen)

parent
5ddce053ea
commit
4dc0d6b2fe
@@ -15,6 +15,10 @@ config SOC_CAPS_ECO_VER_MAX
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int
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default 3
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config SOC_ADC_SUPPORTED
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bool
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default y
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config SOC_DAC_SUPPORTED
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bool
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default y
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@@ -91,6 +95,10 @@ config SOC_ADC_RTC_CTRL_SUPPORTED
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bool
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default y
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config SOC_ADC_DIG_CTRL_SUPPORTED
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bool
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default y
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config SOC_ADC_PERIPH_NUM
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int
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default 2
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@@ -117,11 +125,11 @@ config SOC_ADC_DIGI_MAX_BITWIDTH
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config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
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int
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default 83333
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default 2
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config SOC_ADC_SAMPLE_FREQ_THRES_LOW
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int
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default 611
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default 2000
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config SOC_ADC_MAX_BITWIDTH
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int
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@@ -1,16 +1,8 @@
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// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC_PERIPH_DEFS_H_
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#define _SOC_PERIPH_DEFS_H_
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@@ -54,6 +46,7 @@ typedef enum {
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PERIPH_AES_MODULE,
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PERIPH_SHA_MODULE,
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PERIPH_RSA_MODULE,
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PERIPH_SARADC_MODULE,
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PERIPH_MODULE_MAX
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} periph_module_t;
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@@ -63,6 +63,7 @@
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/*-------------------------- COMMON CAPS ---------------------------------------*/
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#define SOC_CAPS_ECO_VER_MAX 3
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#define SOC_ADC_SUPPORTED 1
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#define SOC_DAC_SUPPORTED 1
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#define SOC_MCPWM_SUPPORTED 1
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#define SOC_SDMMC_HOST_SUPPORTED 1
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@@ -85,7 +86,7 @@
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/*-------------------------- ADC CAPS ----------------------------------------*/
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/**
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* TO BE REMOVED in !14278
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* TO BE REMOVED
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* Check if adc support digital controller (DMA) mode.
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* @value
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* - 1 : support;
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@@ -95,6 +96,7 @@
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/*!< SAR ADC Module*/
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#define SOC_ADC_RTC_CTRL_SUPPORTED 1
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#define SOC_ADC_DIG_CTRL_SUPPORTED 1
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#define SOC_ADC_PERIPH_NUM (2)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 8: 10)
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#define SOC_ADC_MAX_CHANNEL_NUM (10)
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@@ -105,8 +107,8 @@
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#define SOC_ADC_DIGI_MIN_BITWIDTH (9)
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#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
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/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interva <= 4095 */
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#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
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#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
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#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH (2*1000*1000)
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#define SOC_ADC_SAMPLE_FREQ_THRES_LOW (2000)
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/*!< RTC */
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#define SOC_ADC_MAX_BITWIDTH (12)
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