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feat(esp_system): implement hw stack guard for riscv chips

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- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature
This commit is contained in:
Alexey Lapshin
2023-05-04 17:31:31 +02:00
committed by BOT
parent bce88908c7
commit 4df3ff619e
59 changed files with 1299 additions and 230 deletions
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3
components/freertos/test_apps/freertos/sdkconfig.ci.release
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@@ -3,3 +3,6 @@
CONFIG_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_BOOTLOADER_COMPILER_OPTIMIZATION_SIZE=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
# Test if disabled hardware stack guard works as expected (enabled by default)
CONFIG_ESP_SYSTEM_HW_STACK_GUARD=n