feat(esp_system): implement hw stack guard for riscv chips

- add hardware stack guard based on assist-debug module
- enable hardware stack guard by default
- disable hardware stack guard for freertos ci.release test
- refactor rtos_int_enter/rtos_int_exit to change SP register inside them
- fix panic_reason.h header for RISC-V
- update docs to include information about the new feature

tools/test_apps/system/panic/main/test_app_main.c

@@ -83,6 +83,7 @@ void app_main(void)
     HANDLE_TEST(test_name, test_abort_cache_disabled);
     HANDLE_TEST(test_name, test_int_wdt);
     HANDLE_TEST(test_name, test_task_wdt_cpu0);
+    HANDLE_TEST(test_name, test_hw_stack_guard_cpu0);
 #if CONFIG_ESP_COREDUMP_ENABLE_TO_FLASH && CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
     HANDLE_TEST(test_name, test_panic_extram_stack);
 #endif