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feat(esp_system): implement hw stack guard for riscv chips
- add hardware stack guard based on assist-debug module - enable hardware stack guard by default - disable hardware stack guard for freertos ci.release test - refactor rtos_int_enter/rtos_int_exit to change SP register inside them - fix panic_reason.h header for RISC-V - update docs to include information about the new feature
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@@ -52,6 +52,21 @@ CONFIGS_EXTRAM_STACK = [
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pytest.param('coredump_extram_stack', marks=[pytest.mark.esp32, pytest.mark.esp32s2, pytest.mark.psram, pytest.mark.esp32s3, pytest.mark.quad_psram])
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]
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TARGETS_HW_STACK_GUARD = [
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pytest.mark.esp32c2,
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pytest.mark.esp32c3,
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pytest.mark.esp32c6,
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pytest.mark.esp32h2,
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]
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CONFIGS_HW_STACK_GUARD = [
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pytest.param('coredump_flash_bin_crc', marks=TARGETS_HW_STACK_GUARD),
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pytest.param('coredump_uart_bin_crc', marks=TARGETS_HW_STACK_GUARD),
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pytest.param('coredump_uart_elf_crc', marks=TARGETS_HW_STACK_GUARD),
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pytest.param('gdbstub', marks=TARGETS_HW_STACK_GUARD),
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pytest.param('panic', marks=TARGETS_HW_STACK_GUARD),
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]
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def get_default_backtrace(config: str) -> List[str]:
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return [config, 'app_main', 'main_task', 'vPortTaskWrapper']
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@@ -773,3 +788,15 @@ def test_gdbstub_coredump(dut: PanicTestDut) -> None:
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dut.verify_gdb_backtrace(frames, get_default_backtrace(test_func_name))
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dut.revert_log_level()
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return # don't expect "Rebooting" output below
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@pytest.mark.parametrize('config', CONFIGS_HW_STACK_GUARD, indirect=True)
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@pytest.mark.generic
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def test_hw_stack_guard_cpu0(dut: PanicTestDut, config: str, test_func_name: str) -> None:
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dut.run_test_func(test_func_name)
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dut.expect_exact('Guru Meditation Error: Core 0 panic\'ed (Stack protection fault).')
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dut.expect_none('ASSIST_DEBUG is not triggered BUT interrupt occured!')
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dut.expect(r'Detected in task(.*)at 0x')
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dut.expect_exact('Stack pointer: 0x')
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dut.expect(r'Stack bounds: 0x(.*) - 0x')
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common_test(dut, config)
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