mirror of
https://github.com/espressif/esp-idf.git
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soc_cap: add SOC_PM_SUPPORT_VDDSDIO_PD soc_caps
soc_cap: add SOC_PM_CPU_RETENTION_BY_SW/REGDMA soc caps: add SOC_PMU_SUPPORTED
This commit is contained in:
@@ -743,6 +743,10 @@ config SOC_PM_SUPPORT_RC_FAST_PD
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bool
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default y
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config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_CLK_APLL_SUPPORTED
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bool
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default y
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@@ -373,6 +373,7 @@
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#define SOC_PM_SUPPORT_RTC_FAST_MEM_PD (1)
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#define SOC_PM_SUPPORT_RTC_SLOW_MEM_PD (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_APLL_SUPPORTED (1)
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@@ -607,6 +607,10 @@ config SOC_PM_SUPPORT_RC_FAST_PD
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bool
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default y
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config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_CLK_RC_FAST_D256_SUPPORTED
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bool
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default y
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@@ -289,6 +289,7 @@
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#define SOC_PM_SUPPORT_WIFI_PD (0)
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#define SOC_PM_SUPPORT_BT_PD (0)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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/*--------------------------- CLOCK SUBSYSTEM CAPS -------------------------- */
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#define SOC_CLK_RC_FAST_D256_SUPPORTED (1)
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@@ -863,6 +863,14 @@ config SOC_PM_SUPPORT_RC_FAST_PD
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bool
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default y
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config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_PM_CPU_RETENTION_BY_RTCCNTL
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bool
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default y
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config SOC_CLK_RC_FAST_D256_SUPPORTED
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bool
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default y
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@@ -383,6 +383,9 @@
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#define SOC_PM_SUPPORT_WIFI_PD (1)
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#define SOC_PM_SUPPORT_BT_PD (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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#define SOC_PM_CPU_RETENTION_BY_RTCCNTL (1)
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/*--------------------------- CLOCK SUBSYSTEM CAPS -------------------------- */
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#define SOC_CLK_RC_FAST_D256_SUPPORTED (1)
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@@ -147,6 +147,14 @@ config SOC_APM_SUPPORTED
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bool
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default y
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config SOC_PMU_SUPPORTED
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bool
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default y
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config SOC_LP_TIMER_SUPPORTED
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bool
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default y
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config SOC_XTAL_SUPPORT_40M
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bool
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default y
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@@ -659,14 +667,6 @@ config SOC_MCPWM_CLK_SUPPORT_XTAL
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bool
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default y
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config SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH
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int
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default 128
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config SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM
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int
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default 108
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config SOC_RSA_MAX_BIT_LEN
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int
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default 3072
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@@ -963,6 +963,10 @@ config SOC_UART_SUPPORT_XTAL_CLK
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bool
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default y
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config SOC_UART_SUPPORT_WAKEUP_INT
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bool
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default y
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config SOC_UART_SUPPORT_FSM_TX_WAIT_SEND
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bool
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default y
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@@ -991,11 +995,7 @@ config SOC_PM_SUPPORT_CPU_PD
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bool
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default y
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config SOC_PM_SUPPORT_WIFI_PD
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bool
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default y
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config SOC_PM_SUPPORT_BT_PD
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config SOC_PM_SUPPORT_MODEM_PD
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bool
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default y
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@@ -1011,10 +1011,18 @@ config SOC_PM_SUPPORT_RC_FAST_PD
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bool
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default y
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config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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bool
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default y
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config SOC_PM_CPU_RETENTION_BY_SW
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bool
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default y
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config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
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bool
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default y
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@@ -63,6 +63,8 @@
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#define SOC_SDIO_SLAVE_SUPPORTED 1
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#define SOC_BOD_SUPPORTED 1
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#define SOC_APM_SUPPORTED 1
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#define SOC_PMU_SUPPORTED 1
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#define SOC_LP_TIMER_SUPPORTED 1
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/*-------------------------- XTAL CAPS ---------------------------------------*/
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#define SOC_XTAL_SUPPORT_40M 1
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@@ -281,15 +283,6 @@
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#define SOC_MCPWM_CLK_SUPPORT_PLL160M (1) ///< Support PLL160M as clock source
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#define SOC_MCPWM_CLK_SUPPORT_XTAL (1) ///< Support XTAL as clock source
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// TODO: IDF-5348 (Copy from esp32c3, need check)
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/*-------------------------- RTC CAPS --------------------------------------*/
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#define SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH (128)
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#define SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM (108)
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#define SOC_RTC_CNTL_CPU_PD_DMA_ADDR_ALIGN (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
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#define SOC_RTC_CNTL_CPU_PD_DMA_BLOCK_SIZE (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3)
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#define SOC_RTC_CNTL_CPU_PD_RETENTION_MEM_SIZE (SOC_RTC_CNTL_CPU_PD_REG_FILE_NUM * (SOC_RTC_CNTL_CPU_PD_DMA_BUS_WIDTH >> 3))
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// TODO: IDF-5359 (Copy from esp32c3, need check)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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@@ -413,11 +406,10 @@
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#define SOC_UART_NUM (2)
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#define SOC_UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */
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#define SOC_UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */
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#define SOC_UART_SUPPORT_PLL_F80M_CLK (1) /*!< Support PLL_DIV as the clock source */
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#define SOC_UART_SUPPORT_RTC_CLK (1) /*!< Support RTC clock as the clock source */
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#define SOC_UART_SUPPORT_XTAL_CLK (1) /*!< Support XTAL clock as the clock source */
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// #define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: Test UART wakeup while supporting sleep
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#define SOC_UART_SUPPORT_WAKEUP_INT (1) /*!< Support UART wakeup interrupt */ // TODO: Test UART wakeup while supporting sleep
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// UART has an extra TX_WAIT_SEND state when the FIFO is not empty and XOFF is enabled
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#define SOC_UART_SUPPORT_FSM_TX_WAIT_SEND (1)
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@@ -438,14 +430,16 @@
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#define SOC_PM_SUPPORT_WIFI_WAKEUP (1)
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#define SOC_PM_SUPPORT_BT_WAKEUP (1)
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#define SOC_PM_SUPPORT_CPU_PD (1)
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#define SOC_PM_SUPPORT_WIFI_PD (1)
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#define SOC_PM_SUPPORT_BT_PD (1)
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#define SOC_PM_SUPPORT_MODEM_PD (1)
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#define SOC_PM_SUPPORT_XTAL32K_PD (1)
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#define SOC_PM_SUPPORT_RC32K_PD (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
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#define SOC_PM_CPU_RETENTION_BY_SW (1)
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION (1)
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#define SOC_MODEM_CLOCK_IS_INDEPENDENT (1)
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@@ -831,6 +831,14 @@ config SOC_PM_SUPPORT_RC_FAST_PD
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bool
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default y
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config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_PM_CPU_RETENTION_BY_RTCCNTL
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bool
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default y
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config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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bool
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default y
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@@ -419,7 +419,8 @@
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#define SOC_PM_SUPPORT_WIFI_PD (1)
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#define SOC_PM_SUPPORT_BT_PD (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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#define SOC_PM_CPU_RETENTION_BY_RTCCNTL (1)
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#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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@@ -955,6 +955,10 @@ config SOC_PM_SUPPORT_RC_FAST_PD
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bool
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default y
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config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_CLK_APLL_SUPPORTED
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bool
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default y
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@@ -415,6 +415,7 @@
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#define SOC_PM_SUPPORT_RTC_FAST_MEM_PD (1)
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#define SOC_PM_SUPPORT_RTC_SLOW_MEM_PD (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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/*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
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#define SOC_CLK_APLL_SUPPORTED (1)
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@@ -1003,10 +1003,18 @@ config SOC_PM_SUPPORT_RC_FAST_PD
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bool
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default y
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config SOC_PM_SUPPORT_VDDSDIO_PD
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bool
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default y
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config SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY
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bool
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default y
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config SOC_PM_CPU_RETENTION_BY_RTCCNTL
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bool
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default y
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config SOC_CLK_RC_FAST_D256_SUPPORTED
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bool
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default y
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@@ -411,9 +411,12 @@
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#define SOC_PM_SUPPORT_TAGMEM_PD (1)
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#define SOC_PM_SUPPORT_RTC_PERIPH_PD (1)
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#define SOC_PM_SUPPORT_RC_FAST_PD (1)
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#define SOC_PM_SUPPORT_VDDSDIO_PD (1)
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#define SOC_PM_SUPPORT_DEEPSLEEP_CHECK_STUB_ONLY (1) /*!<Supports CRC only the stub code in RTC memory */
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#define SOC_PM_CPU_RETENTION_BY_RTCCNTL (1)
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/*--------------------------- CLOCK SUBSYSTEM CAPS -------------------------- */
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#define SOC_CLK_RC_FAST_D256_SUPPORTED (1)
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#define SOC_RTC_SLOW_CLK_SUPPORT_RC_FAST_D256 (1)
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