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feat(freertos): Added changes for multi-core RISC-V port for FreeRTOS
This commit updates the FreeRTOS port layer for multi-core RISC-V targets.
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@@ -185,8 +185,6 @@
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/*-----------------------------------------------------------*/
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//TODO: IDF-7566
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#if !CONFIG_IDF_TARGET_ESP32P4
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#define taskSELECT_HIGHEST_PRIORITY_TASK() \
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{ \
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UBaseType_t uxTopPriority; \
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@@ -196,17 +194,6 @@
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configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
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listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB[ 0 ], &( pxReadyTasksLists[ uxTopPriority ] ) ); \
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} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
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#else
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#define taskSELECT_HIGHEST_PRIORITY_TASK() \
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{ \
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UBaseType_t uxTopPriority; \
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\
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/* Find the highest priority list that contains ready tasks. */ \
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portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority ); \
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configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 ); \
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listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB[ xPortGetCoreID() ], &( pxReadyTasksLists[ uxTopPriority ] ) ); \
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} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
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#endif
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/*-----------------------------------------------------------*/
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