alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-25 17:58:46 +00:00
Code Issues Packages Projects Releases Wiki Activity

change(uart): change sleep code to be cache safe

Browse Source 
- Set uart ll with FORCE_INLINE_ATTR
- Add no_flash API periph_ll_uart_enabled api
This commit is contained in:
wuzhenghui
2023-06-25 13:43:54 +08:00
parent 6c14e1de9f
commit 4e9cc65763
9 changed files with 241 additions and 134 deletions
Download Patch File Download Diff File Expand all files Collapse all files

15
components/hal/esp32c6/include/hal/clk_gate_ll.h
View File

@@ -8,9 +8,11 @@
#include <stdint.h>
#include <stdbool.h>
#include "hal/assert.h"
#include "soc/periph_defs.h"
#include "soc/pcr_reg.h"
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "esp_attr.h"
#ifdef __cplusplus
@@ -328,6 +330,19 @@ static inline bool IRAM_ATTR periph_ll_periph_enabled(periph_module_t periph)
REG_GET_BIT(periph_ll_get_clk_en_reg(periph), periph_ll_get_clk_en_mask(periph)) != 0;
}
FORCE_INLINE_ATTR bool periph_ll_uart_enabled(uint32_t uart_num)
{
HAL_ASSERT(uart_num < SOC_UART_HP_NUM);
uint32_t uart_clk_config_reg = ((uart_num == 0) ? PCR_UART0_CONF_REG :
(uart_num == 1) ? PCR_UART1_CONF_REG : 0);
uint32_t uart_rst_bit = ((uart_num == 0) ? PCR_UART0_RST_EN :
(uart_num == 1) ? PCR_UART1_RST_EN : 0);
uint32_t uart_en_bit = ((uart_num == 0) ? PCR_UART0_CLK_EN :
(uart_num == 1) ? PCR_UART1_CLK_EN : 0);
return REG_GET_BIT(uart_clk_config_reg, uart_rst_bit) == 0 &&
REG_GET_BIT(uart_clk_config_reg, uart_en_bit) != 0;
}
#ifdef __cplusplus
}
#endif

133
components/hal/esp32c6/include/hal/uart_ll.h
View File

@@ -10,6 +10,7 @@
#pragma once
#include "esp_attr.h"
#include "hal/misc.h"
#include "hal/uart_types.h"
#include "soc/uart_reg.h"
@@ -90,7 +91,7 @@ typedef enum {
* @param hw Beginning address of the peripheral registers.
* @param source_clk Current LP_UART clock source, one in soc_periph_lp_uart_clk_src_t.
*/
static inline void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
FORCE_INLINE_ATTR void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
(void)hw;
switch (LP_CLKRST.lpperi.lp_uart_clk_sel) {
@@ -114,7 +115,7 @@ static inline void lp_uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_
*
* @return None.
*/
static inline void uart_ll_update(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_update(uart_dev_t *hw)
{
hw->reg_update.reg_update = 1;
while (hw->reg_update.reg_update);
@@ -128,7 +129,7 @@ static inline void uart_ll_update(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
FORCE_INLINE_ATTR void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
{
if ((hw) != &LP_UART) {
UART_LL_PCR_REG_SET(hw, conf, rst_en, core_rst_en);
@@ -146,7 +147,7 @@ static inline void uart_ll_set_reset_core(uart_dev_t *hw, bool core_rst_en)
*
* @return None.
*/
static inline void uart_ll_sclk_enable(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_sclk_enable(uart_dev_t *hw)
{
if ((hw) != &LP_UART) {
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 1);
@@ -164,7 +165,7 @@ static inline void uart_ll_sclk_enable(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_sclk_disable(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_sclk_disable(uart_dev_t *hw)
{
if ((hw) != &LP_UART) {
UART_LL_PCR_REG_SET(hw, sclk_conf, sclk_en, 0);
@@ -184,7 +185,7 @@ static inline void uart_ll_sclk_disable(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
FORCE_INLINE_ATTR void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
{
if ((hw) != &LP_UART) {
uint32_t sel_value = 0;
@@ -218,7 +219,7 @@ static inline void uart_ll_set_sclk(uart_dev_t *hw, soc_module_clk_t source_clk)
*
* @return None.
*/
static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk)
{
if ((hw) != &LP_UART) {
switch (UART_LL_PCR_REG_GET(hw, sclk_conf, sclk_sel)) {
@@ -247,7 +248,7 @@ static inline void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source_clk
*
* @return None
*/
static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
@@ -275,7 +276,7 @@ static inline void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t
*
* @return The current baudrate
*/
static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
{
typeof(hw->clkdiv_sync) div_reg;
div_reg.val = hw->clkdiv_sync.val;
@@ -296,7 +297,7 @@ static inline uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_freq)
*
* @return None
*/
static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
FORCE_INLINE_ATTR void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val |= mask;
}
@@ -309,7 +310,7 @@ static inline void uart_ll_ena_intr_mask(uart_dev_t *hw, uint32_t mask)
*
* @return None
*/
static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
FORCE_INLINE_ATTR void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_ena.val &= (~mask);
}
@@ -321,7 +322,7 @@ static inline void uart_ll_disable_intr_mask(uart_dev_t *hw, uint32_t mask)
*
* @return The UART interrupt status.
*/
static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
{
return hw->int_raw.val;
}
@@ -333,7 +334,7 @@ static inline uint32_t uart_ll_get_intraw_mask(uart_dev_t *hw)
*
* @return The UART interrupt status.
*/
static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
{
return hw->int_st.val;
}
@@ -346,7 +347,7 @@ static inline uint32_t uart_ll_get_intsts_mask(uart_dev_t *hw)
*
* @return None
*/
static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
FORCE_INLINE_ATTR void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
{
hw->int_clr.val = mask;
}
@@ -358,7 +359,7 @@ static inline void uart_ll_clr_intsts_mask(uart_dev_t *hw, uint32_t mask)
*
* @return interrupt enable value
*/
static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
{
return hw->int_ena.val;
}
@@ -372,7 +373,7 @@ static inline uint32_t uart_ll_get_intr_ena_status(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
FORCE_INLINE_ATTR void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd_len)
{
for (int i = 0; i < (int)rd_len; i++) {
buf[i] = hw->fifo.rxfifo_rd_byte;
@@ -388,7 +389,7 @@ static inline void uart_ll_read_rxfifo(uart_dev_t *hw, uint8_t *buf, uint32_t rd
*
* @return None
*/
static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
FORCE_INLINE_ATTR void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint32_t wr_len)
{
for (int i = 0; i < (int)wr_len; i++) {
hw->fifo.rxfifo_rd_byte = buf[i];
@@ -402,7 +403,7 @@ static inline void uart_ll_write_txfifo(uart_dev_t *hw, const uint8_t *buf, uint
*
* @return None
*/
static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
{
hw->conf0_sync.rxfifo_rst = 1;
uart_ll_update(hw);
@@ -417,7 +418,7 @@ static inline void uart_ll_rxfifo_rst(uart_dev_t *hw)
*
* @return None
*/
static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
{
hw->conf0_sync.txfifo_rst = 1;
uart_ll_update(hw);
@@ -432,7 +433,7 @@ static inline void uart_ll_txfifo_rst(uart_dev_t *hw)
*
* @return The readable data length in rxfifo.
*/
static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{
return (hw->status.rxfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
}
@@ -444,7 +445,7 @@ static inline uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
*
* @return The data length of txfifo can be written.
*/
static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
{
uint32_t total_fifo_len = ((hw) == &LP_UART) ? LP_UART_LL_FIFO_DEF_LEN : UART_LL_FIFO_DEF_LEN;
uint32_t txfifo_len = (hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw);
@@ -459,7 +460,7 @@ static inline uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
FORCE_INLINE_ATTR void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_bit)
{
hw->conf0_sync.stop_bit_num = stop_bit;
uart_ll_update(hw);
@@ -473,7 +474,7 @@ static inline void uart_ll_set_stop_bits(uart_dev_t *hw, uart_stop_bits_t stop_b
*
* @return None.
*/
static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
FORCE_INLINE_ATTR void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_bit)
{
*stop_bit = (uart_stop_bits_t)hw->conf0_sync.stop_bit_num;
}
@@ -486,7 +487,7 @@ static inline void uart_ll_get_stop_bits(uart_dev_t *hw, uart_stop_bits_t *stop_
*
* @return None.
*/
static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
FORCE_INLINE_ATTR void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
{
if (parity_mode != UART_PARITY_DISABLE) {
hw->conf0_sync.parity = parity_mode & 0x1;
@@ -503,7 +504,7 @@ static inline void uart_ll_set_parity(uart_dev_t *hw, uart_parity_t parity_mode)
*
* @return None.
*/
static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode)
{
if (hw->conf0_sync.parity_en) {
*parity_mode = (uart_parity_t)(0x2 | hw->conf0_sync.parity);
@@ -521,7 +522,7 @@ static inline void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_mode
*
* @return None.
*/
static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
{
hw->conf1.rxfifo_full_thrhd = full_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
}
@@ -535,7 +536,7 @@ static inline void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thr
*
* @return None.
*/
static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
{
hw->conf1.txfifo_empty_thrhd = empty_thrhd << UART_LL_REG_FIELD_BIT_SHIFT(hw);
}
@@ -549,7 +550,7 @@ static inline void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_t
*
* @return None.
*/
static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
FORCE_INLINE_ATTR void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
{
hw->idle_conf_sync.rx_idle_thrhd = rx_idle_thr;
uart_ll_update(hw);
@@ -563,7 +564,7 @@ static inline void uart_ll_set_rx_idle_thr(uart_dev_t *hw, uint32_t rx_idle_thr)
*
* @return None.
*/
static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
{
hw->idle_conf_sync.tx_idle_num = idle_num;
uart_ll_update(hw);
@@ -577,7 +578,7 @@ static inline void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num)
*
* @return None.
*/
static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
{
if (break_num > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->txbrk_conf_sync, tx_brk_num, break_num);
@@ -597,7 +598,7 @@ static inline void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
*
* @return None.
*/
static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t flow_ctrl, uint32_t rx_thrs)
{
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
@@ -622,7 +623,7 @@ static inline void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
*
* @return None.
*/
static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
FORCE_INLINE_ATTR void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_t *flow_ctrl)
{
*flow_ctrl = UART_HW_FLOWCTRL_DISABLE;
if (hw->hwfc_conf_sync.rx_flow_en) {
@@ -642,7 +643,7 @@ static inline void uart_ll_get_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcontrol_
*
* @return None.
*/
static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *flow_ctrl, bool sw_flow_ctrl_en)
{
if (sw_flow_ctrl_en) {
hw->swfc_conf0_sync.xonoff_del = 1;
@@ -671,7 +672,7 @@ static inline void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl_t *
*
* @return None.
*/
static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
{
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, data, cmd_char->cmd_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char_sync, char_num, cmd_char->char_num);
@@ -689,7 +690,7 @@ static inline void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_ch
*
* @return None.
*/
static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
FORCE_INLINE_ATTR void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t data_bit)
{
hw->conf0_sync.bit_num = data_bit;
uart_ll_update(hw);
@@ -703,7 +704,7 @@ static inline void uart_ll_set_data_bit_num(uart_dev_t *hw, uart_word_length_t d
*
* @return None.
*/
static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
FORCE_INLINE_ATTR void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
{
hw->conf0_sync.sw_rts = level & 0x1;
uart_ll_update(hw);
@@ -717,7 +718,7 @@ static inline void uart_ll_set_rts_active_level(uart_dev_t *hw, int level)
*
* @return None.
*/
static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
FORCE_INLINE_ATTR void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
{
hw->conf1.sw_dtr = level & 0x1;
}
@@ -731,7 +732,7 @@ static inline void uart_ll_set_dtr_active_level(uart_dev_t *hw, int level)
*
* @return None.
*/
static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
FORCE_INLINE_ATTR void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
{
hw->sleep_conf2.active_threshold = wakeup_thrd - UART_LL_MIN_WAKEUP_THRESH;
}
@@ -743,7 +744,7 @@ static inline void uart_ll_set_wakeup_thrd(uart_dev_t *hw, uint32_t wakeup_thrd)
*
* @return None.
*/
static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode_normal(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
@@ -763,7 +764,7 @@ static inline void uart_ll_set_mode_normal(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
@@ -787,7 +788,7 @@ static inline void uart_ll_set_mode_rs485_app_ctrl(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
@@ -814,7 +815,7 @@ static inline void uart_ll_set_mode_rs485_half_duplex(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
@@ -839,7 +840,7 @@ static inline void uart_ll_set_mode_collision_detect(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
FORCE_INLINE_ATTR void uart_ll_set_mode_irda(uart_dev_t *hw)
{
// This function is only for HP_UART use
// LP_UART can only work in normal mode
@@ -861,7 +862,7 @@ static inline void uart_ll_set_mode_irda(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
{
switch (mode) {
default:
@@ -896,7 +897,7 @@ static inline void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
*
* @return None.
*/
static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
{
*cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, data);
*char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char_sync, char_num);
@@ -909,7 +910,7 @@ static inline void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, ui
*
* @return The UART wakeup threshold value.
*/
static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
{
return hw->sleep_conf2.active_threshold + UART_LL_MIN_WAKEUP_THRESH;
}
@@ -922,7 +923,7 @@ static inline uint32_t uart_ll_get_wakeup_thrd(uart_dev_t *hw)
*
* @return The bit mode.
*/
static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *data_bit)
{
*data_bit = (uart_word_length_t)hw->conf0_sync.bit_num;
}
@@ -934,7 +935,7 @@ static inline void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length_t *
*
* @return True if the state machine is in the IDLE state, otherwise false is returned.
*/
static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
{
return ((((hw->status.txfifo_cnt) >> UART_LL_REG_FIELD_BIT_SHIFT(hw)) == 0) && (hw->fsm_status.st_utx_out == 0));
}
@@ -946,7 +947,7 @@ static inline bool uart_ll_is_tx_idle(uart_dev_t *hw)
*
* @return True if hw rts flow control is enabled, otherwise false is returned.
*/
static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
FORCE_INLINE_ATTR bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
{
return hw->hwfc_conf_sync.rx_flow_en;
}
@@ -958,7 +959,7 @@ static inline bool uart_ll_is_hw_rts_en(uart_dev_t *hw)
*
* @return True if hw cts flow control is enabled, otherwise false is returned.
*/
static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
FORCE_INLINE_ATTR bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
{
return hw->conf0_sync.tx_flow_en;
}
@@ -971,13 +972,13 @@ static inline bool uart_ll_is_hw_cts_en(uart_dev_t *hw)
*
* @return None
*/
static inline void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
FORCE_INLINE_ATTR void uart_ll_set_loop_back(uart_dev_t *hw, bool loop_back_en)
{
hw->conf0_sync.loopback = loop_back_en;
uart_ll_update(hw);
}
static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
FORCE_INLINE_ATTR void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
{
hw->swfc_conf0_sync.force_xon = 1;
uart_ll_update(hw);
@@ -996,7 +997,7 @@ static inline void uart_ll_xon_force_on(uart_dev_t *hw, bool always_on)
*
* @return None.
*/
static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
FORCE_INLINE_ATTR void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
{
// LP_UART does not support UART_SIGNAL_IRDA_TX_INV and UART_SIGNAL_IRDA_RX_INV
// lp_uart_dev_t has no these fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
@@ -1027,7 +1028,7 @@ static inline void uart_ll_inverse_signal(uart_dev_t *hw, uint32_t inv_mask)
*
* @return None.
*/
static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
FORCE_INLINE_ATTR void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
{
uint16_t tout_val = tout_thrd;
if(tout_thrd > 0) {
@@ -1046,7 +1047,7 @@ static inline void uart_ll_set_rx_tout(uart_dev_t *hw, uint16_t tout_thrd)
*
* @return tout_thr The timeout threshold value. If timeout feature is disabled returns 0.
*/
static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
FORCE_INLINE_ATTR uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
{
uint16_t tout_thrd = 0;
if(hw->tout_conf_sync.rx_tout_en > 0) {
@@ -1062,7 +1063,7 @@ static inline uint16_t uart_ll_get_rx_tout_thr(uart_dev_t *hw)
*
* @return maximum timeout threshold.
*/
static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
FORCE_INLINE_ATTR uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
{
return ((hw) == &LP_UART) ? LP_UART_RX_TOUT_THRHD_V : UART_RX_TOUT_THRHD_V;
}
@@ -1073,7 +1074,7 @@ static inline uint16_t uart_ll_max_tout_thrd(uart_dev_t *hw)
* @param hw Beginning address of the peripheral registers.
* @param enable Boolean marking whether the auto baudrate should be enabled or not.
*/
static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
FORCE_INLINE_ATTR void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
{
// LP_UART does not support autobaud
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
@@ -1087,7 +1088,7 @@ static inline void uart_ll_set_autobaud_en(uart_dev_t *hw, bool enable)
*
* @param hw Beginning address of the peripheral registers.
*/
static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
@@ -1100,7 +1101,7 @@ static inline uint32_t uart_ll_get_rxd_edge_cnt(uart_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers.
*/
static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
@@ -1113,7 +1114,7 @@ static inline uint32_t uart_ll_get_pos_pulse_cnt(uart_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers.
*/
static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
@@ -1126,7 +1127,7 @@ static inline uint32_t uart_ll_get_neg_pulse_cnt(uart_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers.
*/
static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
@@ -1139,7 +1140,7 @@ static inline uint32_t uart_ll_get_high_pulse_cnt(uart_dev_t *hw)
*
* @param hw Beginning address of the peripheral registers.
*/
static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
FORCE_INLINE_ATTR uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
{
// LP_UART does not support this feature
// lp_uart_dev_t has no following fields (reserved), but no harm since we map the LP_UART instance to the uart_dev_t struct
@@ -1154,7 +1155,7 @@ static inline uint32_t uart_ll_get_low_pulse_cnt(uart_dev_t *hw)
*
* @return None.
*/
static inline void uart_ll_force_xoff(uart_port_t uart_num)
FORCE_INLINE_ATTR void uart_ll_force_xoff(uart_port_t uart_num)
{
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
hw->swfc_conf0_sync.force_xon = 0;
@@ -1170,7 +1171,7 @@ static inline void uart_ll_force_xoff(uart_port_t uart_num)
*
* @return None.
*/
static inline void uart_ll_force_xon(uart_port_t uart_num)
FORCE_INLINE_ATTR void uart_ll_force_xon(uart_port_t uart_num)
{
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
hw->swfc_conf0_sync.force_xoff = 0;
@@ -1187,7 +1188,7 @@ static inline void uart_ll_force_xon(uart_port_t uart_num)
*
* @return UART module FSM status.
*/
static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
FORCE_INLINE_ATTR uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
{
uart_dev_t *hw = UART_LL_GET_HW(uart_num);
return hw->fsm_status.st_utx_out;
@@ -1200,7 +1201,7 @@ static inline uint32_t uart_ll_get_fsm_status(uart_port_t uart_num)
* @param discard true: Receiver stops storing data into FIFO when data is wrong
* false: Receiver continue storing data into FIFO when data is wrong
*/
static inline void uart_ll_discard_error_data(uart_dev_t *hw, bool discard)
FORCE_INLINE_ATTR void uart_ll_discard_error_data(uart_dev_t *hw, bool discard)
{
hw->conf0_sync.err_wr_mask = discard ? 1 : 0;
uart_ll_update(hw);