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Power Management: add RTC8M power domain to control whether internal 8m oscillator is powered down during sleep

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This commit is contained in:
Li Shuai
2021-08-27 10:38:55 +08:00
parent d2fa3fd234
commit 4ef6e37fcb
9 changed files with 49 additions and 8 deletions
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4
components/esp_hw_support/port/esp32/rtc_sleep.c
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@@ -194,9 +194,11 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} }
//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK. //Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
if (!cfg.deep_slp && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) { if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD); REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU); REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} else {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} }
/* enable VDDSDIO control by state machine */ /* enable VDDSDIO control by state machine */

10
components/esp_hw_support/port/esp32c3/rtc_sleep.c
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@@ -116,6 +116,16 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT);
} }
//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
} else {
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
}
/* enable VDDSDIO control by state machine */ /* enable VDDSDIO control by state machine */
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);

8
components/esp_hw_support/port/esp32s2/rtc_sleep.c
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@@ -116,6 +116,14 @@ void rtc_sleep_init(rtc_sleep_config_t cfg)
REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT); REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN_DEEP_SLP, RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT);
} }
//Keep the RTC8M_CLK on in light_sleep mode if the ledc low-speed channel is clocked by RTC8M_CLK.
if (!cfg.int_8m_pd_en && GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN_M)) {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PD);
REG_SET_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
} else {
REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
}
/* enable VDDSDIO control by state machine */ /* enable VDDSDIO control by state machine */
REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE); REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en); REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);

3
components/esp_system/include/esp_sleep.h
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@@ -49,7 +49,10 @@ typedef enum {
ESP_PD_DOMAIN_RTC_SLOW_MEM, //!< RTC slow memory ESP_PD_DOMAIN_RTC_SLOW_MEM, //!< RTC slow memory
ESP_PD_DOMAIN_RTC_FAST_MEM, //!< RTC fast memory ESP_PD_DOMAIN_RTC_FAST_MEM, //!< RTC fast memory
ESP_PD_DOMAIN_XTAL, //!< XTAL oscillator ESP_PD_DOMAIN_XTAL, //!< XTAL oscillator
#if SOC_PM_SUPPORT_CPU_PD
ESP_PD_DOMAIN_CPU, //!< CPU core ESP_PD_DOMAIN_CPU, //!< CPU core
#endif
ESP_PD_DOMAIN_RTC8M, //!< Internal 8M oscillator
ESP_PD_DOMAIN_VDDSDIO, //!< VDD_SDIO ESP_PD_DOMAIN_VDDSDIO, //!< VDD_SDIO
ESP_PD_DOMAIN_MAX //!< Number of domains ESP_PD_DOMAIN_MAX //!< Number of domains
} esp_sleep_pd_domain_t; } esp_sleep_pd_domain_t;

15
components/esp_system/sleep_modes.c
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@@ -154,7 +154,13 @@ typedef struct {
} sleep_config_t; } sleep_config_t;
static sleep_config_t s_config = { static sleep_config_t s_config = {
.pd_options = { ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO }, .pd_options = {
ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO,
#if SOC_PM_SUPPORT_CPU_PD
ESP_PD_OPTION_AUTO,
#endif
ESP_PD_OPTION_AUTO, ESP_PD_OPTION_AUTO
},
.ccount_ticks_record = 0, .ccount_ticks_record = 0,
.sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US, .sleep_time_overhead_out = DEFAULT_SLEEP_OUT_OVERHEAD_US,
.wakeup_triggers = 0 .wakeup_triggers = 0
@@ -1312,10 +1318,6 @@ static uint32_t get_power_down_flags(void)
if (s_config.cpu_pd_mem == NULL) { if (s_config.cpu_pd_mem == NULL) {
s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON; s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON;
} }
#else
if (s_config.pd_options[ESP_PD_DOMAIN_CPU] != ESP_PD_OPTION_ON) {
s_config.pd_options[ESP_PD_DOMAIN_CPU] = ESP_PD_OPTION_ON;
}
#endif #endif
if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) { if (s_config.pd_options[ESP_PD_DOMAIN_XTAL] == ESP_PD_OPTION_AUTO) {
@@ -1348,6 +1350,9 @@ static uint32_t get_power_down_flags(void)
pd_flags |= RTC_SLEEP_PD_CPU; pd_flags |= RTC_SLEEP_PD_CPU;
} }
#endif #endif
if (s_config.pd_options[ESP_PD_DOMAIN_RTC8M] != ESP_PD_OPTION_ON) {
pd_flags |= RTC_SLEEP_PD_INT_8M;
}
#ifdef CONFIG_IDF_TARGET_ESP32 #ifdef CONFIG_IDF_TARGET_ESP32
pd_flags |= RTC_SLEEP_PD_XTAL; pd_flags |= RTC_SLEEP_PD_XTAL;

4
components/soc/esp32/include/soc/rtc.h
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@@ -493,6 +493,7 @@ typedef struct rtc_sleep_config_s {
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM uint32_t rom_mem_pd_en : 1; //!< power down main RAM and ROM
uint32_t deep_slp : 1; //!< power down digital domain uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
@@ -513,6 +514,7 @@ typedef struct rtc_sleep_config_s {
* *
* @param RTC_SLEEP_PD_x flags combined using bitwise OR * @param RTC_SLEEP_PD_x flags combined using bitwise OR
*/ */
#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG)
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ #define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 0, \ .lslp_mem_inf_fpu = 0, \
.rtc_mem_inf_fpu = 0, \ .rtc_mem_inf_fpu = 0, \
@@ -521,6 +523,7 @@ typedef struct rtc_sleep_config_s {
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = 0, \ .wifi_pd_en = 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.rom_mem_pd_en = 0, \ .rom_mem_pd_en = 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \ .wdt_flashboot_mod_en = 0, \
@@ -540,6 +543,7 @@ typedef struct rtc_sleep_config_s {
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL #define RTC_SLEEP_PD_XTAL BIT(6) //!< Power down main XTAL
#define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator
/* Various delays to be programmed into power control state machines */ /* Various delays to be programmed into power control state machines */
#define RTC_CNTL_XTL_BUF_WAIT_SLP_US (500) #define RTC_CNTL_XTL_BUF_WAIT_SLP_US (500)

4
components/soc/esp32c3/include/soc/rtc.h
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@@ -639,6 +639,7 @@ typedef struct {
uint32_t wifi_pd_en : 1; //!< power down WiFi uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t bt_pd_en : 1; //!< power down BT uint32_t bt_pd_en : 1; //!< power down BT
uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep. uint32_t cpu_pd_en : 1; //!< power down CPU, but not restart when lightsleep.
uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals uint32_t dig_peri_pd_en : 1; //!< power down digital peripherals
uint32_t deep_slp : 1; //!< power down digital domain uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
@@ -659,6 +660,7 @@ typedef struct {
* *
* @param RTC_SLEEP_PD_x flags combined using bitwise OR * @param RTC_SLEEP_PD_x flags combined using bitwise OR
*/ */
#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG)
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ #define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 0, \ .lslp_mem_inf_fpu = 0, \
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
@@ -668,6 +670,7 @@ typedef struct {
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \ .bt_pd_en = ((sleep_flags) & RTC_SLEEP_PD_BT) ? 1 : 0, \
.cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \ .cpu_pd_en = ((sleep_flags) & RTC_SLEEP_PD_CPU) ? 1 : 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \ .dig_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_DIG_PERIPH) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \ .wdt_flashboot_mod_en = 0, \
@@ -690,6 +693,7 @@ typedef struct {
#define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT #define RTC_SLEEP_PD_BT BIT(7) //!< Power down BT
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart #define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals #define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
/** /**
* @brief Prepare the chip to enter sleep mode * @brief Prepare the chip to enter sleep mode

4
components/soc/esp32s2/include/soc/rtc.h
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@@ -654,6 +654,7 @@ typedef struct {
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
uint32_t wifi_pd_en : 1; //!< power down WiFi uint32_t wifi_pd_en : 1; //!< power down WiFi
uint32_t int_8m_pd_en : 1; //!< Power down Internal 8M oscillator
uint32_t deep_slp : 1; //!< power down digital domain uint32_t deep_slp : 1; //!< power down digital domain
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode
@@ -673,6 +674,7 @@ typedef struct {
* *
* @param RTC_SLEEP_PD_x flags combined using bitwise OR * @param RTC_SLEEP_PD_x flags combined using bitwise OR
*/ */
#define is_dslp(pd_flags) ((pd_flags) & RTC_SLEEP_PD_DIG)
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ #define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
.lslp_mem_inf_fpu = 0, \ .lslp_mem_inf_fpu = 0, \
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
@@ -680,6 +682,7 @@ typedef struct {
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
.int_8m_pd_en = is_dslp(sleep_flags) ? 1 : ((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? 1 : 0, \
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
.wdt_flashboot_mod_en = 0, \ .wdt_flashboot_mod_en = 0, \
.dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \ .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
@@ -698,6 +701,7 @@ typedef struct {
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_WIFI BIT(6) #define RTC_SLEEP_PD_WIFI BIT(6)
#define RTC_SLEEP_PD_INT_8M BIT(7) //!< Power down Internal 8M oscillator
/** /**
* @brief Prepare the chip to enter sleep mode * @brief Prepare the chip to enter sleep mode

1
components/soc/esp32s3/include/soc/rtc.h
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@@ -672,6 +672,7 @@ typedef struct {
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU #define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator #define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
#define RTC_SLEEP_PD_WIFI BIT(6) #define RTC_SLEEP_PD_WIFI BIT(6)
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
/** /**
* @brief Prepare the chip to enter sleep mode * @brief Prepare the chip to enter sleep mode