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apll: add lock for apll

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This commit is contained in:
laokaiyao
2021-12-02 20:24:19 +08:00
parent af4e448928
commit 4f28b33bbc
18 changed files with 406 additions and 222 deletions
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40
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@@ -191,10 +191,34 @@ config SOC_I2C_SUPPORT_APB
bool
default y
config SOC_CLK_APLL_SUPPORTED
bool
default y
config SOC_APLL_MULTIPLIER_OUT_MIN_HZ
int
default 350000000
config SOC_APLL_MULTIPLIER_OUT_MAX_HZ
int
default 500000000
config SOC_APLL_MIN_HZ
int
default 5303031
config SOC_APLL_MAX_HZ
int
default 125000000
config SOC_I2S_NUM
int
default 2
config SOC_I2S_SUPPORTS_APLL
bool
default y
config SOC_I2S_SUPPORTS_PDM_TX
bool
default y
@@ -211,22 +235,6 @@ config SOC_I2S_SUPPORTS_DAC
bool
default y
config SOC_I2S_SUPPORTS_APLL
bool
default y
config SOC_I2S_APLL_MIN_FREQ
int
default 250000000
config SOC_I2S_APLL_MAX_FREQ
int
default 500000000
config SOC_I2S_APLL_MIN_RATE
int
default 10675
config SOC_I2S_TRANS_SIZE_ALIGN_WORD
bool
default y

33
components/soc/esp32/include/soc/rtc.h
View File

@@ -46,10 +46,6 @@ extern "C" {
* - rtc_init: initialization
*/
/* APLL frequency range */
#define RTC_APLL_FREQ_MAX 128000000 // 128MHz
#define RTC_APLL_FREQ_MIN 16000000 // 16MHz
/**
* @brief Possible main XTAL frequency values.
*
@@ -255,22 +251,33 @@ bool rtc_clk_8md256_enabled(void);
* In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
*
* @param enable true to enable, false to disable
*/
void rtc_clk_apll_enable(bool enable);
/**
* @brief Calculate APLL clock coeffifcients
*
* @param freq expected APLL frequency
* @param o_div frequency divider, 0..31
* @param sdm0 frequency adjustment parameter, 0..255
* @param sdm1 frequency adjustment parameter, 0..255
* @param sdm2 frequency adjustment parameter, 0..63
* @param o_div frequency divider, 0..31
*
* @return
* - 0 Failed
* - else Sucess
*/
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1,
uint32_t sdm2, uint32_t o_div);
uint32_t rtc_clk_apll_coeff_calc(uint32_t freq, uint32_t *_o_div, uint32_t *_sdm0, uint32_t *_sdm1, uint32_t *_sdm2);
/**
* @brief Set APLL clock freqency
* @param freq Expected APLL freqency (unit: Hz)
* @return
* - 0: Failed, the expected APLL frequency is out of range
* - else: The true APLL clock (unit: Hz)
* @brief Set APLL clock coeffifcients
*
* @param o_div frequency divider, 0..31
* @param sdm0 frequency adjustment parameter, 0..255
* @param sdm1 frequency adjustment parameter, 0..255
* @param sdm2 frequency adjustment parameter, 0..63
*/
uint32_t rtc_clk_apll_freq_set(uint32_t freq);
void rtc_clk_apll_coeff_set(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2);
/**
* @brief Select source for RTC_SLOW_CLK

15
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -157,18 +157,23 @@
#define SOC_I2C_SUPPORT_APB (1)
/*-------------------------- APLL CAPS ----------------------------------------*/
#define SOC_CLK_APLL_SUPPORTED (1)
// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
#define SOC_APLL_MULTIPLIER_OUT_MIN_HZ (350000000) // 350 MHz
#define SOC_APLL_MULTIPLIER_OUT_MAX_HZ (500000000) // 500 MHz
#define SOC_APLL_MIN_HZ (5303031) // 5.303031 MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
#define SOC_APLL_MAX_HZ (125000000) // 125MHz, refer to 'periph_rtc_apll_freq_set' for the calculation
/*-------------------------- I2S CAPS ----------------------------------------*/
// ESP32 have 2 I2S
#define SOC_I2S_NUM (2)
#define SOC_I2S_NUM (2U)
#define SOC_I2S_SUPPORTS_APLL (1) // ESP32 support APLL
#define SOC_I2S_SUPPORTS_PDM_TX (1)
#define SOC_I2S_SUPPORTS_PDM_RX (1)
#define SOC_I2S_SUPPORTS_ADC (1) // ESP32 support ADC and DAC
#define SOC_I2S_SUPPORTS_DAC (1)
#define SOC_I2S_SUPPORTS_APLL (1)// ESP32 support APLL
#define SOC_I2S_APLL_MIN_FREQ (250000000)
#define SOC_I2S_APLL_MAX_FREQ (500000000)
#define SOC_I2S_APLL_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
#define SOC_I2S_TRANS_SIZE_ALIGN_WORD (1) // I2S DMA transfer size must be aligned to word
#define SOC_I2S_LCD_I80_VARIANT (1) // I2S has a special LCD mode that can generate Intel 8080 TX timing