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fix(bootloader): fixed P4 bootloader being able to boot with certain configs

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Due to internal memory being behind a cache on P4 we need to make sure we do
cache write backs when manipulating IRAM over the dcache.
This commit is contained in:
Marius Vikhammer
2024-03-07 17:19:56 +08:00
parent c8651c1041
commit 503b917ca5
3 changed files with 12 additions and 8 deletions
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13
components/bootloader_support/src/esp_image_format.c
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@@ -226,6 +226,8 @@ static esp_err_t image_load(esp_image_load_mode_t mode, const esp_partition_pos_
}
}
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
/* We have manipulated data over dcache that will be read over icache and need
to writeback, else the data read might be invalid */
cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
#endif
}
@@ -673,6 +675,13 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
if (checksum == NULL && sha_handle == NULL) {
memcpy((void *)load_addr, data, data_len);
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
if (esp_ptr_in_iram((uint32_t *)load_addr)) {
/* If we have manipulated data over dcache that will be read over icache then we need
to writeback, else the data read might be invalid */
cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
}
#endif
bootloader_munmap(data);
return ESP_OK;
}
@@ -728,7 +737,9 @@ static esp_err_t process_segment_data(int segment, intptr_t load_addr, uint32_t
}
}
#if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
if (do_load && esp_ptr_in_diram_iram((uint32_t *)load_addr)) {
if (do_load && esp_ptr_in_iram((uint32_t *)load_addr)) {
/* If we have manipulated data over dcache that will be read over icache then we need
to writeback, else the data read might be invalid */
cache_ll_writeback_all(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA, CACHE_LL_ID_ALL);
}
#endif