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gpio: Fix io hold functionality on esp32c6 and esp32h2

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This commit is contained in:
Song Ruo Jing
2023-02-26 23:09:02 +08:00
committed by wuzhenghui
parent 7ee64bd8e8
commit 51777a6862
13 changed files with 78 additions and 78 deletions
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42
components/hal/esp32c6/include/hal/gpio_ll.h
View File

@@ -21,7 +21,7 @@
#include "soc/gpio_struct.h"
#include "soc/lp_aon_struct.h"
#include "soc/lp_io_struct.h"
#include "soc/pmu_reg.h"
#include "soc/pmu_struct.h"
#include "soc/usb_serial_jtag_reg.h"
#include "soc/pcr_struct.h"
#include "soc/clk_tree_defs.h"
@@ -355,26 +355,6 @@ static inline void gpio_ll_get_drive_capability(gpio_dev_t *hw, uint32_t gpio_nu
*strength = (gpio_drive_cap_t)GET_PERI_REG_BITS2(IO_MUX_GPIO0_REG + (gpio_num * 4), FUN_DRV_V, FUN_DRV_S);
}
/**
* @brief Enable all digital gpio pads hold function during Deep-sleep.
*
* @param hw Peripheral GPIO hardware instance address.
*/
static inline void gpio_ll_deep_sleep_hold_en(gpio_dev_t *hw)
{
REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_HIGH_HP_PAD_HOLD_ALL);
}
/**
* @brief Disable all digital gpio pads hold function during Deep-sleep.
*
* @param hw Peripheral GPIO hardware instance address.
*/
static inline void gpio_ll_deep_sleep_hold_dis(gpio_dev_t *hw)
{
REG_SET_BIT(PMU_IMM_PAD_HOLD_ALL_REG, PMU_TIE_LOW_HP_PAD_HOLD_ALL);
}
/**
* @brief Enable gpio pad hold function.
*
@@ -497,6 +477,26 @@ static inline void gpio_ll_iomux_set_clk_src(soc_module_clk_t src)
}
}
/**
* @brief Force hold digital io pad.
* @note GPIO force hold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_hold_all(void)
{
// WT flag, it gets self-cleared after the configuration is done
PMU.imm.pad_hold_all.tie_high_hp_pad_hold_all = 1;
}
/**
* @brief Force unhold digital io pad.
* @note GPIO force unhold, whether the chip in sleep mode or wakeup mode.
*/
static inline void gpio_ll_force_unhold_all(void)
{
// WT flag, it gets self-cleared after the configuration is done
PMU.imm.pad_hold_all.tie_low_hp_pad_hold_all = 1;
}
/**
* @brief Enable GPIO pin to use sleep mode pin functions during light sleep.
*

24
components/hal/esp32c6/include/hal/rtc_io_ll.h
View File

@@ -30,8 +30,6 @@ extern "C" {
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_PIN_MASK_ALL ((1 << SOC_RTCIO_PIN_COUNT) - 1)
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
@@ -244,22 +242,6 @@ static inline void rtcio_ll_force_hold_disable(int rtcio_num)
LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num);
}
/**
* @brief Enable all LP IO pads hold function during Deep-sleep
*/
static inline void rtcio_ll_deep_sleep_hold_en_all(void)
{
PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
}
/**
* @brief Disable all LP IO pads hold function during Deep-sleep
*/
static inline void rtcio_ll_deep_sleep_hold_dis_all(void)
{
PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
}
/**
* Enable force hold function for all RTC IO pads
*
@@ -270,8 +252,7 @@ static inline void rtcio_ll_deep_sleep_hold_dis_all(void)
*/
static inline void rtcio_ll_force_hold_all(void)
{
// No such a 'hold_all' bit on C6, use bit hold instead
LP_AON.gpio_hold0.gpio_hold0 |= RTCIO_LL_PIN_MASK_ALL;
PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
}
/**
@@ -281,8 +262,7 @@ static inline void rtcio_ll_force_hold_all(void)
*/
static inline void rtcio_ll_force_unhold_all(void)
{
// No such a 'hold_all' bit on C6, use bit hold instead
LP_AON.gpio_hold0.gpio_hold0 &= ~RTCIO_LL_PIN_MASK_ALL;
PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
}
/**