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gpio: Fix io hold functionality on esp32c6 and esp32h2

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This commit is contained in:
Song Ruo Jing
2023-02-26 23:09:02 +08:00
committed by wuzhenghui
parent 7ee64bd8e8
commit 51777a6862
13 changed files with 78 additions and 78 deletions
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24
components/hal/esp32c6/include/hal/rtc_io_ll.h
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@@ -30,8 +30,6 @@ extern "C" {
#define RTCIO_LL_PIN_FUNC 0
#define RTCIO_LL_PIN_MASK_ALL ((1 << SOC_RTCIO_PIN_COUNT) - 1)
typedef enum {
RTCIO_FUNC_RTC = 0x0, /*!< The pin controlled by RTC module. */
RTCIO_FUNC_DIGITAL = 0x1, /*!< The pin controlled by DIGITAL module. */
@@ -244,22 +242,6 @@ static inline void rtcio_ll_force_hold_disable(int rtcio_num)
LP_AON.gpio_hold0.gpio_hold0 &= ~BIT(rtcio_num);
}
/**
* @brief Enable all LP IO pads hold function during Deep-sleep
*/
static inline void rtcio_ll_deep_sleep_hold_en_all(void)
{
PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
}
/**
* @brief Disable all LP IO pads hold function during Deep-sleep
*/
static inline void rtcio_ll_deep_sleep_hold_dis_all(void)
{
PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
}
/**
* Enable force hold function for all RTC IO pads
*
@@ -270,8 +252,7 @@ static inline void rtcio_ll_deep_sleep_hold_dis_all(void)
*/
static inline void rtcio_ll_force_hold_all(void)
{
// No such a 'hold_all' bit on C6, use bit hold instead
LP_AON.gpio_hold0.gpio_hold0 |= RTCIO_LL_PIN_MASK_ALL;
PMU.imm.pad_hold_all.tie_high_lp_pad_hold_all = 1;
}
/**
@@ -281,8 +262,7 @@ static inline void rtcio_ll_force_hold_all(void)
*/
static inline void rtcio_ll_force_unhold_all(void)
{
// No such a 'hold_all' bit on C6, use bit hold instead
LP_AON.gpio_hold0.gpio_hold0 &= ~RTCIO_LL_PIN_MASK_ALL;
PMU.imm.pad_hold_all.tie_low_lp_pad_hold_all = 1;
}
/**