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adc: support ADC on esp32c6 (driver/test/example)
This commit is contained in:
laokaiyao
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -20,6 +20,7 @@
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#include "hal/adc_types.h"
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#include "hal/adc_types_private.h"
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#include "hal/regi2c_ctrl.h"
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#include "hal/sar_ctrl_ll.h"
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#include "soc/regi2c_saradc.h"
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@@ -36,49 +37,30 @@ extern "C" {
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#define ADC_LL_EVENT_ADC1_ONESHOT_DONE BIT(31)
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#define ADC_LL_EVENT_ADC2_ONESHOT_DONE BIT(30)
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#define ADC_LL_EVENT_THRES0_HIGH BIT(29)
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#define ADC_LL_event_THRES1_HIGH BIT(28)
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#define ADC_LL_event_THRES0_LOW BIT(27)
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#define ADC_LL_EVENT_THRES1_HIGH BIT(28)
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#define ADC_LL_EVENT_THRES0_LOW BIT(27)
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#define ADC_LL_EVENT_THRES1_LOW BIT(26)
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typedef enum {
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ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
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ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */
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ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */
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ADC_POWER_BY_FSM = SAR_CTRL_LL_POWER_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
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ADC_POWER_SW_ON = SAR_CTRL_LL_POWER_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */
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ADC_POWER_SW_OFF = SAR_CTRL_LL_POWER_OFF, /*!< ADC XPD controlled by SW. power off. */
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ADC_POWER_MAX, /*!< For parameter check. */
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} adc_ll_power_t;
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typedef enum {
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ADC_RTC_DATA_OK = 0,
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ADC_RTC_CTRL_UNSELECTED = 1,
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ADC_RTC_CTRL_BREAK = 2,
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ADC_RTC_DATA_FAIL = -1,
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} adc_ll_rtc_raw_data_t;
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typedef enum {
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ADC_LL_CTRL_DIG = 0, ///< Only support ADC1, i.e. only digital controller available.
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ADC_LL_CTRL_DIG = 0, ///< ADC digital controller
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} adc_ll_controller_t;
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/**
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* @brief Clock source of ADC digital controller
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* @note Not public as it always uses a default value for now
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*/
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typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t;
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/**
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* @brief Clock source of ADC digital controller
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* @note Not public as it always uses a default value for now
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*/
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typedef soc_periph_adc_digi_clk_src_t adc_ll_digi_clk_src_t;
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/**
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* @brief ADC digital controller (DMA mode) work mode.
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*
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* @note The conversion mode affects the sampling frequency:
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* ESP32C3 only support ALTER_UNIT mode
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* ALTER_UNIT : When the measurement is triggered, ADC1 or ADC2 samples alternately.
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* ESP32C6 only support ONLY_ADC1 mode
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* SINGLE_UNIT_1: When the measurement is triggered, only ADC1 is sampled once.
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*/
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typedef enum {
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ADC_LL_DIGI_CONV_ALTER_UNIT = 0, // Use both ADC1 and ADC2 for conversion by turn. e.g. ADC1 -> ADC2 -> ADC1 -> ADC2 .....
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ADC_LL_DIGI_CONV_ONLY_ADC1 = 0, // Only use ADC1 for conversion
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} adc_ll_digi_convert_mode_t;
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typedef struct {
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@@ -123,9 +105,7 @@ static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wa
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*/
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static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
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{
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// TODO: [adc_c6] Maybe this REG I2C for peripheral needs a reference lock
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/* Should be called before writing I2C registers. */
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SET_PERI_REG_MASK(PMU_RF_PWC_REG, PMU_XPD_PERIF_I2C);
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/* Peripheral reg i2c has powered up in rtc_init, write directly */
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_SAMPLE_CYCLE_ADDR, sample_cycle);
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}
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@@ -137,7 +117,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
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*/
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static inline void adc_ll_digi_set_clk_div(uint32_t div)
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{
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/* ADC clock devided from digital controller clock clk */
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/* ADC clock divided from digital controller clock clk */
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HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.saradc_ctrl, saradc_saradc_sar_clk_div, div);
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}
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@@ -166,18 +146,18 @@ static inline void adc_ll_digi_convert_limit_enable(bool enable)
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/**
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* Set adc conversion mode for digital controller.
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*
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* @note ESP32C3 only support ADC1 single mode.
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* @note ESP32C6 only support ADC1 single mode.
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*
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* @param mode Conversion mode select.
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*/
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static inline void adc_ll_digi_set_convert_mode(adc_ll_digi_convert_mode_t mode)
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{
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//ESP32C3 only supports ADC_CONV_ALTER_UNIT mode
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//ESP32C6 only supports ADC_LL_DIGI_CONV_ONLY_ADC1 mode
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}
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/**
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* Set pattern table length for digital controller.
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* The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection,
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* The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection,
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* and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
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* pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself.
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*
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@@ -191,7 +171,7 @@ static inline void adc_ll_digi_set_pattern_table_len(adc_unit_t adc_n, uint32_t
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/**
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* Set pattern table for digital controller.
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* The pattern table that defines the conversion rules for each SAR ADC. Each table has 8 items, in which channel selection,
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* The pattern table that defines the conversion rules for each SAR ADC. Each table has 4 items, in which channel selection,
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* resolution and attenuation are stored. When the conversion is started, the controller reads conversion rules from the
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* pattern table one by one. For each controller the scan sequence has at most 8 different rules before repeating itself.
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*
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@@ -208,15 +188,15 @@ static inline void adc_ll_digi_set_pattern_table(adc_unit_t adc_n, uint32_t patt
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pattern.val = (table.atten & 0x3) | ((table.channel & 0x7) << 2) | ((table.unit & 0x1) << 5);
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if (index == 0) {
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tab = APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1; // Read old register value
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tab &= (~(0xFC0000 >> offset)); // Clear old data
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tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data
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APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = tab; // Write back
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tab = APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1; // Read old register value
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tab &= (~(0xFC0000 >> offset)); // Clear old data
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tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data
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APB_SARADC.saradc_sar_patt_tab1.saradc_saradc_sar_patt_tab1 = tab; // Write back
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} else {
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tab = APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2; // Read old register value
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tab &= (~(0xFC0000 >> offset)); // Clear old data
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tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data
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APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = tab; // Write back
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tab = APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2; // Read old register value
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tab &= (~(0xFC0000 >> offset)); // Clear old data
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tab |= ((uint32_t)(pattern.val & 0x3F) << 18) >> offset; // Fill in the new data
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APB_SARADC.saradc_sar_patt_tab2.saradc_saradc_sar_patt_tab2 = tab; // Write back
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}
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}
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@@ -252,8 +232,6 @@ static inline void adc_ll_digi_output_invert(adc_unit_t adc_n, bool inv_en)
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{
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if (adc_n == ADC_UNIT_1) {
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APB_SARADC.saradc_ctrl2.saradc_saradc_sar1_inv = inv_en; // Enable / Disable ADC data invert
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} else { // adc_n == ADC_UNIT_2
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APB_SARADC.saradc_ctrl2.saradc_saradc_sar2_inv = inv_en; // Enable / Disable ADC data invert
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}
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}
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@@ -305,7 +283,7 @@ static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div
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*
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* @param clk_src clock source for ADC digital controller.
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*/
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static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src)
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static inline void adc_ll_digi_clk_sel(adc_continuous_clk_src_t clk_src)
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{
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switch (clk_src) {
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case ADC_DIGI_CLK_SRC_XTAL:
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@@ -318,10 +296,10 @@ static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src)
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PCR.saradc_clkm_conf.saradc_clkm_sel = 2;
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break;
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default:
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PCR.saradc_clkm_conf.saradc_clkm_sel = 1;
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HAL_ASSERT(false && "unsupported clock");
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}
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// Enable ADC_CTRL_CLK (i.e. digital domain clock)
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PCR.saradc_clkm_conf.saradc_clkm_en = 1;
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
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}
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/**
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@@ -329,7 +307,7 @@ static inline void adc_ll_digi_clk_sel(adc_ll_digi_clk_src_t clk_src)
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*/
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static inline void adc_ll_digi_controller_clk_disable(void)
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{
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PCR.saradc_clkm_conf.saradc_clkm_en = 0;
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0;
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}
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/**
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@@ -480,9 +458,7 @@ static inline void adc_ll_digi_reset(void)
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*/
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static inline void adc_ll_pwdet_set_cct(uint32_t cct)
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{
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/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
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// RTCCNTL.sensor_ctrl.sar2_pwdet_cct = cct;
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// TODO: [adc_c6] check cct validation on C6
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(void)cct;
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}
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/**
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@@ -493,9 +469,6 @@ static inline void adc_ll_pwdet_set_cct(uint32_t cct)
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*/
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static inline uint32_t adc_ll_pwdet_get_cct(void)
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{
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/* Capacitor tuning of the PA power monitor. cct set to the same value with PHY. */
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// return RTCCNTL.sensor_ctrl.sar2_pwdet_cct;
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// TODO: [adc_c6] check cct validation on C6
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return 0;
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}
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@@ -512,13 +485,13 @@ static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
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/* Bit1 0:Fsm 1: SW mode
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Bit0 0:SW mode power down 1: SW mode power on */
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if (manage == ADC_POWER_SW_ON) {
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PCR.saradc_clkm_conf.saradc_clkm_en = 1;
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
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APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 3;
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} else if (manage == ADC_POWER_BY_FSM) {
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PCR.saradc_clkm_conf.saradc_clkm_en = 1;
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 1;
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APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 0;
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} else if (manage == ADC_POWER_SW_OFF) {
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PCR.saradc_clkm_conf.saradc_clkm_en = 0;
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APB_SARADC.saradc_ctrl.saradc_saradc_sar_clk_gated = 0;
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APB_SARADC.saradc_ctrl.saradc_saradc_xpd_sar_force = 2;
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}
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}
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@@ -536,11 +509,8 @@ static inline void adc_ll_set_controller(adc_unit_t adc_n, adc_ll_controller_t c
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__attribute__((always_inline))
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static inline void adc_ll_calibration_init(adc_unit_t adc_n)
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{
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if (adc_n == ADC_UNIT_1) {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1);
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} else {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_DREF_ADDR, 1);
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}
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_DREF_ADDR, 1);
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}
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/**
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@@ -554,19 +524,12 @@ static inline void adc_ll_calibration_init(adc_unit_t adc_n)
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*/
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static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, bool internal_gnd)
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{
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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/* Enable/disable internal connect GND (for calibration). */
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if (adc_n == ADC_UNIT_1) {
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if (internal_gnd) {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
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} else {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
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}
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if (internal_gnd) {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 1);
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} else {
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if (internal_gnd) {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 1);
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} else {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
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}
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
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}
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}
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@@ -577,11 +540,8 @@ static inline void adc_ll_calibration_prepare(adc_unit_t adc_n, bool internal_gn
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*/
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static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
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{
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if (adc_n == ADC_UNIT_1) {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
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} else {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_ENCAL_GND_ADDR, 0);
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}
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_ENCAL_GND_ADDR, 0);
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}
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/**
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@@ -594,17 +554,12 @@ static inline void adc_ll_calibration_finish(adc_unit_t adc_n)
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__attribute__((always_inline))
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static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param)
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{
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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uint8_t msb = param >> 8;
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uint8_t lsb = param & 0xFF;
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if (adc_n == ADC_UNIT_1) {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
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} else {
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_HIGH_ADDR, msb);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR2_INITIAL_CODE_LOW_ADDR, lsb);
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}
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_HIGH_ADDR, msb);
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REGI2C_WRITE_MASK(I2C_SAR_ADC, ADC_SAR1_INITIAL_CODE_LOW_ADDR, lsb);
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}
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/* Temp code end. */
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/*---------------------------------------------------------------
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Oneshot Read
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@@ -612,13 +567,13 @@ static inline void adc_ll_set_calibration_param(adc_unit_t adc_n, uint32_t param
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/**
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* Set adc output data format for oneshot mode
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*
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* @note ESP32C3 Oneshot mode only supports 12bit.
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* @note ESP32C6 Oneshot mode only supports 12bit.
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* @param adc_n ADC unit.
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* @param bits Output data bits width option.
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*/
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static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth_t bits)
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{
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//ESP32C3 only supports 12bit, leave here for compatibility
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//ESP32C6 only supports 12bit, leave here for compatibility
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HAL_ASSERT(bits == ADC_BITWIDTH_12 || bits == ADC_BITWIDTH_DEFAULT);
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}
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@@ -632,6 +587,7 @@ static inline void adc_oneshot_ll_set_output_bits(adc_unit_t adc_n, adc_bitwidth
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*/
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static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t channel)
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{
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | channel);
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}
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@@ -644,11 +600,8 @@ static inline void adc_oneshot_ll_set_channel(adc_unit_t adc_n, adc_channel_t ch
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*/
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static inline void adc_oneshot_ll_disable_channel(adc_unit_t adc_n)
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{
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if (adc_n == ADC_UNIT_1) {
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APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF);
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} else { // adc_n == ADC_UNIT_2
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APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0x1);
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}
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HAL_ASSERT(adc_n == ADC_UNIT_1);
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APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_channel = ((adc_n << 3) | 0xF);
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}
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/**
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@@ -688,7 +641,7 @@ static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
|
||||
}
|
||||
|
||||
/**
|
||||
* Get the converted value for each ADCn for RTC controller.
|
||||
* Get the converted value for each ADCn for controller.
|
||||
*
|
||||
* @param adc_n ADC unit.
|
||||
* @return
|
||||
@@ -696,12 +649,9 @@ static inline bool adc_oneshot_ll_get_event(uint32_t event_mask)
|
||||
*/
|
||||
static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
|
||||
{
|
||||
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
||||
uint32_t ret_val = 0;
|
||||
if (adc_n == ADC_UNIT_1) {
|
||||
ret_val = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff;
|
||||
} else { // adc_n == ADC_UNIT_2
|
||||
ret_val = APB_SARADC.saradc_sar2data_status.saradc_apb_saradc2_data & 0xfff;
|
||||
}
|
||||
ret_val = APB_SARADC.saradc_sar1data_status.saradc_apb_saradc1_data & 0xfff;
|
||||
return ret_val;
|
||||
}
|
||||
|
||||
@@ -717,15 +667,7 @@ static inline uint32_t adc_oneshot_ll_get_raw_result(adc_unit_t adc_n)
|
||||
*/
|
||||
static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw_data)
|
||||
{
|
||||
if (adc_n == ADC_UNIT_1) {
|
||||
return true;
|
||||
}
|
||||
|
||||
//The raw data API returns value without channel information. Read value directly from the register
|
||||
if (((APB_SARADC.saradc_sar2data_status.saradc_apb_saradc2_data >> 13) & 0xF) > 9) {
|
||||
return false;
|
||||
}
|
||||
|
||||
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
||||
return true;
|
||||
}
|
||||
|
||||
@@ -737,7 +679,7 @@ static inline bool adc_oneshot_ll_raw_check_valid(adc_unit_t adc_n, uint32_t raw
|
||||
*/
|
||||
static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en)
|
||||
{
|
||||
(void)adc_n;
|
||||
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
||||
(void)inv_en;
|
||||
//For compatibility
|
||||
}
|
||||
@@ -749,11 +691,8 @@ static inline void adc_oneshot_ll_output_invert(adc_unit_t adc_n, bool inv_en)
|
||||
*/
|
||||
static inline void adc_oneshot_ll_enable(adc_unit_t adc_n)
|
||||
{
|
||||
if (adc_n == ADC_UNIT_1) {
|
||||
APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1;
|
||||
} else {
|
||||
APB_SARADC.saradc_onetime_sample.saradc_saradc2_onetime_sample = 1;
|
||||
}
|
||||
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
||||
APB_SARADC.saradc_onetime_sample.saradc_saradc1_onetime_sample = 1;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -776,7 +715,7 @@ static inline void adc_oneshot_ll_disable_all_unit(void)
|
||||
*/
|
||||
static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t channel, adc_atten_t atten)
|
||||
{
|
||||
(void)adc_n;
|
||||
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
||||
(void)channel;
|
||||
// Attenuation is for all channels, unit and channel are for compatibility
|
||||
APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten = atten;
|
||||
@@ -792,7 +731,7 @@ static inline void adc_oneshot_ll_set_atten(adc_unit_t adc_n, adc_channel_t chan
|
||||
__attribute__((always_inline))
|
||||
static inline adc_atten_t adc_ll_get_atten(adc_unit_t adc_n, adc_channel_t channel)
|
||||
{
|
||||
(void)adc_n;
|
||||
HAL_ASSERT(adc_n == ADC_UNIT_1);
|
||||
(void)channel;
|
||||
return (adc_atten_t)APB_SARADC.saradc_onetime_sample.saradc_saradc_onetime_atten;
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user