Merge branch 'feature/lp_core_40_mhz' into 'master'

feat(system): support choosing xtal as rtc-fast clock src on P4 and C5

Closes IDF-10203

See merge request espressif/esp-idf!32450

components/ulp/lp_core/lp_core/lp_core_utils.c

@@ -30,7 +30,17 @@
 #include "esp_cpu.h"
 
 /* LP_FAST_CLK is not very accurate, for now use a rough estimate */
+#if CONFIG_RTC_FAST_CLK_SRC_RC_FAST
 #define LP_CORE_CPU_FREQUENCY_HZ 16000000 // For P4 TRM says 20 MHz by default, but we tune it closer to 16 MHz
+#elif CONFIG_RTC_FAST_CLK_SRC_XTAL
+#if SOC_XTAL_SUPPORT_48M
+#define LP_CORE_CPU_FREQUENCY_HZ 48000000
+#else
+#define LP_CORE_CPU_FREQUENCY_HZ 40000000
+#endif
+#else  // Default value in chip without rtc fast clock sel option
+#define LP_CORE_CPU_FREQUENCY_HZ 16000000
+#endif
 
 static uint32_t lp_wakeup_cause = 0;
 

components/ulp/test_apps/.build-test-rules.yml

@@ -1,6 +1,11 @@
 # Documentation: .gitlab/ci/README.md#manifest-file-to-control-the-buildtest-apps
 
-components/ulp/test_apps/lp_core:
+components/ulp/test_apps/lp_core/lp_core_basic_tests:
+  disable:
+    - if: SOC_LP_CORE_SUPPORTED != 1
+    - if: CONFIG_NAME == "xtal" and SOC_CLK_LP_FAST_SUPPORT_XTAL != 1
+
+components/ulp/test_apps/lp_core/lp_core_hp_uart:
   disable:
     - if: SOC_LP_CORE_SUPPORTED != 1
 

components/ulp/test_apps/lp_core/lp_core_basic_tests/main/test_lp_core.c

@@ -132,6 +132,7 @@ TEST_CASE("Test LP core delay", "[lp_core]")
 #define LP_TIMER_TEST_SLEEP_DURATION_US (20000)
 
 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
+#if SOC_DEEP_SLEEP_SUPPORTED && CONFIG_RTC_FAST_CLK_SRC_RC_FAST
 
 static void do_ulp_wakeup_deepsleep(lp_core_test_commands_t ulp_cmd)
 {
@@ -228,7 +229,8 @@ TEST_CASE_MULTIPLE_STAGES("LP Timer can wakeup lp core periodically during deep
                           do_ulp_wakeup_with_lp_timer_deepsleep,
                           check_reset_reason_and_sleep_duration);
 
-#endif //#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
+#endif //#if SOC_DEEP_SLEEP_SUPPORTED && CONFIG_RTC_FAST_CLK_SRC_RC_FAST
+#endif //!TEMPORARY_DISABLED_FOR_TARGETS(ESP32C5)
 
 TEST_CASE("LP Timer can wakeup lp core periodically", "[lp_core]")
 {
@@ -382,5 +384,4 @@ TEST_CASE("LP core ISR tests", "[ulp]")
     printf("ULP LP IO ISR triggered %"PRIu32" times\n", ulp_io_isr_counter);
     TEST_ASSERT_EQUAL(ISR_TEST_ITERATIONS, ulp_io_isr_counter);
 #endif //SOC_RTCIO_PIN_COUNT > 0
-
 }

components/ulp/test_apps/lp_core/lp_core_basic_tests/pytest_lp_core_basic.py

@@ -8,10 +8,31 @@ from pytest_embedded import Dut
 @pytest.mark.esp32c6
 @pytest.mark.esp32p4
 @pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'default',
+    ],
+    indirect=True,
+)
 def test_lp_core(dut: Dut) -> None:
     dut.run_all_single_board_cases()
 
 
+@pytest.mark.esp32c5
+@pytest.mark.esp32p4
+@pytest.mark.generic
+@pytest.mark.parametrize(
+    'config',
+    [
+        'xtal',
+    ],
+    indirect=True,
+)
+def test_lp_core_xtal(dut: Dut) -> None:
+    dut.run_all_single_board_cases()
+
+
 @pytest.mark.esp32c6
 # TODO: Enable LP I2C test for esp32p4 (IDF-9407)
 @pytest.mark.generic_multi_device

components/ulp/test_apps/lp_core/lp_core_basic_tests/sdkconfig.ci.xtal

@@ -0,0 +1 @@
+CONFIG_RTC_FAST_CLK_SRC_XTAL=y