Fix the clock subsystem so it doesn't undo the weird condition spiram_psram.c jams the enable/reset bits of SPI3 in when 80MHz mode is selected anymore

components/esp32/clk.c

@@ -219,10 +219,7 @@ void esp_perip_clk_init(void)
                               DPORT_LEDC_CLK_EN |
                               DPORT_UHCI1_CLK_EN |
                               DPORT_TIMERGROUP1_CLK_EN |
-//80MHz SPIRAM uses SPI2 as well; it's initialized before this is called. Do not disable the clock for that if this is enabled.
-#if !CONFIG_SPIRAM_SPEED_80M
                               DPORT_SPI_CLK_EN_2 |
-#endif
                               DPORT_PWM0_CLK_EN |
                               DPORT_I2C_EXT1_CLK_EN |
                               DPORT_CAN_CLK_EN |
@@ -244,6 +241,15 @@ void esp_perip_clk_init(void)
                               DPORT_WIFI_CLK_EMAC_EN;
     }
 
+
+#if CONFIG_SPIRAM_SPEED_80M
+//80MHz SPIRAM uses SPI2 as well; it's initialized before this is called. Because it is used in
+//a weird mode where clock to the peripheral is disabled but reset is also disabled, it 'hangs'
+//in a state where it outputs a continuous 80MHz signal. Mask its bit here because we should
+//not modify that state, regardless of what we calculated earlier.
+    common_perip_clk &= ~DPORT_SPI_CLK_EN_2;
+#endif
+
     /* Change I2S clock to audio PLL first. Because if I2S uses 160MHz clock,
      * the current is not reduced when disable I2S clock.
      */