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Power Management: add XTAL power domain to control whether external 40MHz xtal is powered down during sleep

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This commit is contained in:
Li Shuai
2021-09-06 14:17:43 +08:00
parent f5b39a7cde
commit 58292a7d22
8 changed files with 24 additions and 11 deletions
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3
components/soc/esp32c3/include/soc/rtc.h
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@@ -650,6 +650,7 @@ typedef struct {
uint32_t rtc_dbias_wak : 5; //!< set bias for RTC domain, in active mode
uint32_t rtc_dbias_slp : 5; //!< set bias for RTC domain, in sleep mode
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
uint32_t xtal_fpu : 1; //!< keep main XTAL powered up in sleep
uint32_t deep_slp_reject : 1;
uint32_t light_slp_reject : 1;
} rtc_sleep_config_t;
@@ -685,6 +686,7 @@ typedef struct {
: !((sleep_flags) & RTC_SLEEP_PD_INT_8M) ? RTC_CNTL_DBIAS_1V10 \
: RTC_CNTL_DBIAS_SLP, \
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
.xtal_fpu = is_dslp(sleep_flags) ? 0 : ((sleep_flags) & RTC_SLEEP_PD_XTAL) ? 0 : 1, \
.deep_slp_reject = 1, \
.light_slp_reject = 1 \
};
@@ -700,6 +702,7 @@ typedef struct {
#define RTC_SLEEP_PD_CPU BIT(8) //!< Power down CPU when in lightsleep, but not restart
#define RTC_SLEEP_PD_DIG_PERIPH BIT(9) //!< Power down DIG peripherals
#define RTC_SLEEP_PD_INT_8M BIT(10) //!< Power down Internal 8M oscillator
#define RTC_SLEEP_PD_XTAL BIT(11) //!< Power down main XTAL
/**
* @brief Prepare the chip to enter sleep mode