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docs: Provide CN translation for documents under api-reference

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shenmengjing
2024-03-28 11:14:56 +08:00
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30
docs/en/api-reference/peripherals/spi_flash/spi_flash_idf_vs_rom.rst
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@@ -1,10 +1,12 @@
SPI Flash API ESP-IDF Version vs Chip-ROM Version
===================================================
:link_to_translation:`zh_CN:[中文]`
.. toctree::
:maxdepth: 1
There is a set of SPI Flash drivers in Chip-ROM which you can use by enabling :ref:`CONFIG_SPI_FLASH_ROM_IMPL`. Most of the ESP-IDF SPI Flash driver code are in internal RAM, therefore enabling this option frees some internal RAM usage. Note if you enable this option, this means some SPI Flash driver features and bugfixes that are done in ESP-IDF might not be included in the Chip-ROM version.
There is a set of SPI flash drivers in Chip-ROM which you can use by enabling :ref:`CONFIG_SPI_FLASH_ROM_IMPL`. Most of the ESP-IDF SPI flash driver code are in internal RAM, therefore enabling this option frees some internal RAM usage. Note that if you enable this option, this means some SPI flash driver features and bugfixes that are done in ESP-IDF might not be included in the Chip-ROM version.
Feature Supported by ESP-IDF but Not in Chip-ROM
@@ -12,27 +14,27 @@ Feature Supported by ESP-IDF but Not in Chip-ROM
.. list::
- Octal Flash chip support. See :ref:`oct-flash-doc` for details.
- 32-bit-address support for GD25Q256. Note this feature is an optional feature, please do read :ref:`32-bit-flash-doc` for details.
- TH Flash chip support.
- Octal flash chip support. See :ref:`oct-flash-doc` for details.
- 32-bit-address support for GD25Q256. Note that this feature is an optional feature, please do read :ref:`32-bit-flash-doc` for details.
- TH flash chip support.
- Kconfig option :ref:`CONFIG_SPI_FLASH_CHECK_ERASE_TIMEOUT_DISABLED`.
- :ref:`CONFIG_SPI_FLASH_VERIFY_WRITE`, enabling this option helps you detect bad writing.
- :ref:`CONFIG_SPI_FLASH_LOG_FAILED_WRITE`, enabling this option prints the bad writing.
- :ref:`CONFIG_SPI_FLASH_WARN_SETTING_ZERO_TO_ONE`, enabling this option checks if you are writing zero to one.
- :ref:`CONFIG_SPI_FLASH_DANGEROUS_WRITE`, enabling this option checks for flash programming to certain protected regions like bootloader, partition table or application itself.
- :ref:`CONFIG_SPI_FLASH_ENABLE_COUNTERS`, enabling this option to collect performance data for ESP-IDF SPI Flash driver APIs.
- :ref:`CONFIG_SPI_FLASH_AUTO_SUSPEND`, enabling this option to automatically suspend / resume a long Flash operation when short Flash operation happens. Note this feature is an optional feature, please do read :ref:`auto-suspend-intro` for more limitations.
- :ref:`CONFIG_SPI_FLASH_ENABLE_COUNTERS`, enabling this option to collect performance data for ESP-IDF SPI flash driver APIs.
- :ref:`CONFIG_SPI_FLASH_AUTO_SUSPEND`, enabling this option to automatically suspend or resume a long flash operation when short flash operation happens. Note that this feature is an optional feature, please do read :ref:`auto-suspend-intro` for more limitations.
Bugfixes Introduced in ESP-IDF but Not in Chip-ROM
--------------------------------------------------
.. list::
- Detected Flash physical size correctly, for larger than 256MBit Flash chips. (Commit ID: b4964279d44f73cce7cfd5cf684567fbdfd6fd9e)
:esp32c3: - Improved SPI1 cs setup timing, otherwise issue may happen on ZB32Q128. (Commit ID: 08f1bbe0c75382f1702e40c941e93314285105d4)
:esp32s3: - Fixed issue that 4-line Flash encryption cannot work normally when 8-line PSRAM enabled. (Commit ID: 683d92bc884e0f2a7eebea40a551cf05f0c28256)
:esp32s2: - Fixed issue that only 4MB virtual address ranges can be mapped to read-only data on Flash.
:esp32s3: - Fixed issue that only 128KB virtual address ranges can be mapped to instructions on Flash.
:esp32s3: - Fixed issue that only 16MB virtual address ranges can be mapped to read-only data on Flash.
:esp32c3: - Fixed issue that only 128KB virtual address ranges can be mapped to instructions on Flash.
:esp32c2: - Fixed issue that only at most 128KB virtual address ranges can be mapped to instructions on Flash.
- Detected flash physical size correctly, for larger than 256 MBit flash chips. (Commit ID: b4964279d44f73cce7cfd5cf684567fbdfd6fd9e)
:esp32c3: - Improved SPI1 CS setup timing, otherwise issue may happen on ZB32Q128. (Commit ID: 08f1bbe0c75382f1702e40c941e93314285105d4)
:esp32s3: - Fixed issue that 4-line flash encryption can not work normally when 8-line PSRAM enabled. (Commit ID: 683d92bc884e0f2a7eebea40a551cf05f0c28256)
:esp32s2: - Fixed issue that only 4 MB virtual address ranges can be mapped to read-only data on flash.
:esp32s3: - Fixed issue that only 128 KB virtual address ranges can be mapped to instructions on flash.
:esp32s3: - Fixed issue that only 16 MB virtual address ranges can be mapped to read-only data on flash.
:esp32c3: - Fixed issue that only 128 KB virtual address ranges can be mapped to instructions on flash.
:esp32c2: - Fixed issue that only at most 128 KB virtual address ranges can be mapped to instructions on flash.

4
docs/en/api-reference/system/ulp_macros.rst
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@@ -1,6 +1,8 @@
Programming ULP FSM Coprocessor Using C Macros (Legacy)
=======================================================
:link_to_translation:`zh_CN:[中文]`
In addition to the existing binutils port for the {IDF_TARGET_NAME} ULP coprocessor, it is possible to generate programs for the ULP FSM coprocessor by embedding assembly-like macros into an {IDF_TARGET_NAME} application. Here is an example how this can be done::
const ulp_insn_t program[] = {
@@ -25,7 +27,7 @@ The ``program`` array is an array of ``ulp_insn_t``, i.e., ULP coprocessor instr
.. note::
Load, store and move instructions use **addresses expressed in 32-bit words**. Address 0 corresponds to the first word of ``RTC_SLOW_MEM``.
This is different to how address arguments are handled in assembly code of the same instructions. See the section :ref:`ulp-fsm-addressing` for more details for reference.
This is different from how address arguments are handled in assembly code of the same instructions. See the section :ref:`ulp-fsm-addressing` for more details for reference.
To generate branch instructions, special ``M_`` preprocessor defines are used. ``M_LABEL`` define can be used to define a branch target. Label identifier is a 16-bit integer. ``M_Bxxx`` defines can be used to generate branch instructions with target set to a particular label.