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Merge branch 'feature/disable_rom_logging' into 'master'

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esp32/sleep: Add a function to disable logging from ROM code

See merge request idf/esp-idf!3182
This commit is contained in:
Ivan Grokhotkov
2018-09-06 16:11:23 +08:00
parent 5c3ca78a07 dbad72e6b5
commit 599da58070
7 changed files with 25 additions and 6 deletions
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6
components/esp32/include/esp_sleep.h
View File

@@ -319,6 +319,12 @@ esp_deep_sleep_wake_stub_fn_t esp_get_deep_sleep_wake_stub(void);
*/
void esp_default_wake_deep_sleep(void);
/**
* @brief Disable logging from the ROM code after deep sleep.
*
* Using LSB of RTC_STORE4.
*/
void esp_deep_sleep_disable_rom_logging(void);
#ifdef __cplusplus
}

3
components/esp32/include/rom/rtc.h
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@@ -55,7 +55,7 @@ extern "C" {
* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
* RTC_CNTL_STORE2_REG Boot time, low word
* RTC_CNTL_STORE3_REG Boot time, high word
* RTC_CNTL_STORE4_REG External XTAL frequency
* RTC_CNTL_STORE4_REG External XTAL frequency. The frequency must necessarily be even, otherwise there will be a conflict with the low bit, which is used to disable logs in the ROM code.
* RTC_CNTL_STORE5_REG APB bus frequency
* RTC_CNTL_STORE6_REG FAST_RTC_MEMORY_ENTRY
* RTC_CNTL_STORE7_REG FAST_RTC_MEMORY_CRC
@@ -71,6 +71,7 @@ extern "C" {
#define RTC_RESET_CAUSE_REG RTC_CNTL_STORE6_REG
#define RTC_MEMORY_CRC_REG RTC_CNTL_STORE7_REG
#define RTC_DISABLE_ROM_LOG ((1 << 0) | (1 << 16)) //!< Disable logging from the ROM code.
typedef enum {
AWAKE = 0, //<CPU ON

10
components/esp32/sleep_modes.c
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@@ -658,3 +658,13 @@ static uint32_t get_power_down_flags()
}
return pd_flags;
}
void esp_deep_sleep_disable_rom_logging(void)
{
/* To disable logging in the ROM, only the least significant bit of the register is used,
* but since this register is also used to store the frequency of the main crystal (RTC_XTAL_FREQ_REG),
* you need to write to this register in the same format.
* Namely, the upper 16 bits and lower should be the same.
*/
REG_SET_BIT(RTC_CNTL_STORE4_REG, RTC_DISABLE_ROM_LOG);
}