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efuse: Update efuses for esp32 esp32c2 esp32c3 esp32s2 esp32s3

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KonstantinKondrashov
2023-02-16 16:22:34 +08:00
parent ab5d8d0008
commit 5b00d1f396
35 changed files with 24034 additions and 11164 deletions
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1363
components/efuse/esp32s2/esp_efuse_table.c
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361
components/efuse/esp32s2/esp_efuse_table.csv
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@@ -1,163 +1,212 @@
# field_name, | efuse_block, | bit_start, | bit_count, |comment #
# | (EFUSE_BLK0 | (0..255) | (1..-) | #
# | EFUSE_BLK1 | |MAX_BLK_LEN*| #
# | ... | | | #
# | EFUSE_BLK10)| | | #
# | (EFUSE_BLK0 | (0..255) | (1-256) | #
# | EFUSE_BLK1 | | | #
# | ...) | | | #
##########################################################################
# *) The value MAX_BLK_LEN depends on CONFIG_EFUSE_MAX_BLK_LEN, will be replaced with "None" - 256. "3/4" - 192. "REPEAT" - 128.
# !!!!!!!!!!! #
# After editing this file, run the command manually "make efuse_common_table" or "idf.py efuse-common-table"
# After editing this file, run the command manually "idf.py efuse-common-table"
# this will generate new source files, next rebuild all the sources.
# !!!!!!!!!!! #
# EFUSE_RD_REPEAT_DATA BLOCK #
##############################
# EFUSE_RD_WR_DIS_REG #
WR_DIS, EFUSE_BLK0, 0, 32, Write protection
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, Write protection for RD_DIS.KEY0 RD_DIS.KEY1 RD_DIS.KEY2 RD_DIS.KEY3 RD_DIS.KEY4 RD_DIS.KEY5 RD_DIS.SYS_DATA_PART2
WR_DIS.DIS_RTC_RAM_BOOT, EFUSE_BLK0, 1, 1, Write protection for DIS_RTC_RAM_BOOT
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
WR_DIS.GROUP_1, EFUSE_BLK0, 2, 1, Write protection for DIS_ICACHE DIS_DCACHE DIS_DOWNLOAD_ICACHE DIS_DOWNLOAD_DCACHE DIS_FORCE_DOWNLOAD DIS_USB DIS_CAN DIS_BOOT_REMAP SOFT_DIS_JTAG HARD_DIS.JTAG DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.GROUP_2, EFUSE_BLK0, 3, 1, Write protection for VDD_SPI_XPD VDD_SPI_TIEH VDD_SPI_FORCE VDD_SPI_INIT VDD_SPI_DCAP WDT_DELAY_SEL
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, Write protection for SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0,EFUSE_BLK0, 5, 1, Write protection for SECURE_BOOT_KEY_REVOKE0
WR_DIS.SECURE_BOOT_KEY_REVOKE1,EFUSE_BLK0, 6, 1, Write protection for SECURE_BOOT_KEY_REVOKE1
WR_DIS.SECURE_BOOT_KEY_REVOKE2,EFUSE_BLK0, 7, 1, Write protection for SECURE_BOOT_KEY_REVOKE2
WR_DIS.KEY0_PURPOSE, EFUSE_BLK0, 8, 1, Write protection for key_purpose. KEY0
WR_DIS.KEY1_PURPOSE, EFUSE_BLK0, 9, 1, Write protection for key_purpose. KEY1
WR_DIS.KEY2_PURPOSE, EFUSE_BLK0, 10, 1, Write protection for key_purpose. KEY2
WR_DIS.KEY3_PURPOSE, EFUSE_BLK0, 11, 1, Write protection for key_purpose. KEY3
WR_DIS.KEY4_PURPOSE, EFUSE_BLK0, 12, 1, Write protection for key_purpose. KEY4
WR_DIS.KEY5_PURPOSE, EFUSE_BLK0, 13, 1, Write protection for key_purpose. KEY5
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, Write protection for SECURE_BOOT_EN
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE,EFUSE_BLK0, 16, 1, Write protection for SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.GROUP_3, EFUSE_BLK0, 18, 1, Write protection for FLASH_TPUW DIS_DOWNLOAD_MODE DIS_LEGACY_SPI_BOOT UART_PRINT_CHANNEL DIS_USB_DOWNLOAD_MODE ENABLE_SECURITY_DOWNLOAD UART_PRINT_CONTROL PIN_POWER_SELECTION FLASH_TYPE FORCE_SEND_RESUME SECURE_VERSION
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, Write protection for EFUSE_BLK1. MAC_SPI_8M_SYS
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, Write protection for EFUSE_BLK2. SYS_DATA_PART1
WR_DIS.USER_DATA, EFUSE_BLK0, 22, 1, Write protection for EFUSE_BLK3. USER_DATA
WR_DIS.KEY0, EFUSE_BLK0, 23, 1, Write protection for EFUSE_BLK4. KEY0
WR_DIS.KEY1, EFUSE_BLK0, 24, 1, Write protection for EFUSE_BLK5. KEY1
WR_DIS.KEY2, EFUSE_BLK0, 25, 1, Write protection for EFUSE_BLK6. KEY2
WR_DIS.KEY3, EFUSE_BLK0, 26, 1, Write protection for EFUSE_BLK7. KEY3
WR_DIS.KEY4, EFUSE_BLK0, 27, 1, Write protection for EFUSE_BLK8. KEY4
WR_DIS.KEY5, EFUSE_BLK0, 28, 1, Write protection for EFUSE_BLK9. KEY5
WR_DIS.SYS_DATA_PART2, EFUSE_BLK0, 29, 1, Write protection for EFUSE_BLK10. SYS_DATA_PART2
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, Write protection for USB_EXCHG_PINS
# This file was generated by regtools.py based on the efuses.yaml file with the version: 888a61f6f500d9c7ee0aa32016b0bee7
# EFUSE_RD_REPEAT_DATA0_REG #
RD_DIS, EFUSE_BLK0, 32, 7, Read protection
RD_DIS.KEY0, EFUSE_BLK0, 32, 1, Read protection for EFUSE_BLK4. KEY0
RD_DIS.KEY1, EFUSE_BLK0, 33, 1, Read protection for EFUSE_BLK5. KEY1
RD_DIS.KEY2, EFUSE_BLK0, 34, 1, Read protection for EFUSE_BLK6. KEY2
RD_DIS.KEY3, EFUSE_BLK0, 35, 1, Read protection for EFUSE_BLK7. KEY3
RD_DIS.KEY4, EFUSE_BLK0, 36, 1, Read protection for EFUSE_BLK8. KEY4
RD_DIS.KEY5, EFUSE_BLK0, 37, 1, Read protection for EFUSE_BLK9. KEY5
RD_DIS.SYS_DATA_PART2, EFUSE_BLK0, 38, 1, Read protection for EFUSE_BLK10. SYS_DATA_PART2
DIS_RTC_RAM_BOOT, EFUSE_BLK0, 39, 1, Disable boot from RTC RAM
DIS_ICACHE, EFUSE_BLK0, 40, 1, Disable Icache
DIS_DCACHE, EFUSE_BLK0, 41, 1, Disable Dcace
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, Disable Icache in download mode include boot_mode 0 1 2 3 6 7
DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, Disable Dcache in download mode include boot_mode 0 1 2 3 6 7
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, Disable force chip go to download mode function
DIS_USB, EFUSE_BLK0, 45, 1, Disable USB function
DIS_CAN, EFUSE_BLK0, 46, 1, Disable CAN function
DIS_BOOT_REMAP, EFUSE_BLK0, 47, 1, Disable boot from RAM. REMAP means RAM space can be mapped to ROM space. this signal will disable this function
SOFT_DIS_JTAG, EFUSE_BLK0, 49, 1, Software disable jtag jtag can be activated again by hmac module
HARD_DIS_JTAG, EFUSE_BLK0, 50, 1, Hardware disable jtag permanently disable jtag function
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 51, 1, Disable flash encrypt function, other than SPI/Legacy SPI boot mode
USB_EXCHG_PINS, EFUSE_BLK0, 56, 1, Exchange D+ D- pins
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 57, 1, Enable external PHY
BLOCK0_VERSION, EFUSE_BLK0, 59, 2, BLOCK0 efuse version
# EFUSE_RD_REPEAT_DATA1_REG #
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, VDD_SPI regulator power up
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, VDD_SPI regulator tie high to vdda
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, Force using eFuse configuration of VDD_SPI
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, Select RTC WDT time out threshold
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, SPI boot encrypt decrypt enable. odd number 1 enable. even number 1 disable
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, Enable revoke first secure boot key
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, Enable revoke second secure boot key
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, Enable revoke third secure boot key
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, Key0 purpose
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, Key1 purpose
# EFUSE_RD_REPEAT_DATA2_REG #
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, Key2 purpose
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, Key3 purpose
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, Key4 purpose
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, Key5 purpose
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, Secure boot enable
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, Enable aggressive secure boot revoke
FLASH_TPUW, EFUSE_BLK0, 124, 4, Flash wait time after power up. (unit is ms). When value is 15. the time is 30 ms
# EFUSE_RD_REPEAT_DATA3_REG #
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, Disble download mode include boot_mode[3:0] is 0 1 2 3 6 7
DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, Disable_Legcy_SPI_boot mode include boot_mode[3:0] is 4
UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, 0: UART0. 1: UART1
DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, Disable download through USB
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, Enable security download mode
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, b00:force print. b01:control by GPIO46 - low level print. b10:control by GPIO46 - high level print. b11:force disable print.
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, GPIO33-GPIO37 power supply selection in ROM code. 0:VDD3P3_CPU. 1:VDD_SPI.
FLASH_TYPE, EFUSE_BLK0, 137, 1, Connected Flash interface type. 0: 4 data line. 1: 8 data line
FORCE_SEND_RESUME, EFUSE_BLK0, 138, 1, Force ROM code to send a resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 139, 16, Secure version for anti-rollback
# EFUSE_RD_REPEAT_DATA4_REG #
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, Disables check of blk version major
# MAC_SPI_8M_SYS BLOCK#
#######################
# RD_MAC_SPI_8M_0 - RD_MAC_SPI_8M_2
MAC_FACTORY, EFUSE_BLK1, 40, 8, Factory MAC addr [0]
, EFUSE_BLK1, 32, 8, Factory MAC addr [1]
, EFUSE_BLK1, 24, 8, Factory MAC addr [2]
, EFUSE_BLK1, 16, 8, Factory MAC addr [3]
, EFUSE_BLK1, 8, 8, Factory MAC addr [4]
, EFUSE_BLK1, 0, 8, Factory MAC addr [5]
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, SPI_PAD_configure CLK
SPI_PAD_CONFIG_Q_D1, EFUSE_BLK1, 54, 6, SPI_PAD_configure Q(D1)
SPI_PAD_CONFIG_D_D0, EFUSE_BLK1, 60, 6, SPI_PAD_configure D(D0)
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, SPI_PAD_configure CS
SPI_PAD_CONFIG_HD_D3, EFUSE_BLK1, 72, 6, SPI_PAD_configure HD(D3)
SPI_PAD_CONFIG_WP_D2, EFUSE_BLK1, 78, 6, SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, SPI_PAD_configure D4
# RD_MAC_SPI_8M_3
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, SPI_PAD_configure D5
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, SPI_PAD_configure D7
WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, WAFER_VERSION_MAJOR
WAFER_VERSION_MINOR, EFUSE_BLK1, 132, 3, WAFER_VERSION_MINOR least significant bits
, EFUSE_BLK1, 116, 1, WAFER_VERSION_MINOR most significant bit
# WAFER_VERSION_MINOR least significant bits is from RD_MAC_SPI_8M_4
FLASH_VERSION, EFUSE_BLK1, 117, 4, Flash_version
BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, BLK_VERSION_MAJOR
PSRAM_VERSION, EFUSE_BLK1, 124, 4, PSRAM version
# RD_MAC_SPI_8M_4
PKG_VERSION, EFUSE_BLK1, 128, 4, Package version
# WAFER_VERSION_MINOR least significant bits
# SYS_DATA_PART1 BLOCK# - System configuration
#######################
# RD_SYS_DATA0 - RD_SYS_DATA3
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, Optional unique 128-bit ID
# RD_SYS_DATA4
BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, BLK_VERSION_MINOR of BLOCK2: 0-No ADC calib; 1-ADC calib V1; 2-ADC calib V2
################
USER_DATA, EFUSE_BLK3, 0, 256, User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, Custom MAC
################
KEY0, EFUSE_BLK4, 0, 256, Key0 or user data
KEY1, EFUSE_BLK5, 0, 256, Key1 or user data
KEY2, EFUSE_BLK6, 0, 256, Key2 or user data
KEY3, EFUSE_BLK7, 0, 256, Key3 or user data
KEY4, EFUSE_BLK8, 0, 256, Key4 or user data
KEY5, EFUSE_BLK9, 0, 256, Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, System configuration
WR_DIS, EFUSE_BLK0, 0, 32, [] Disable programming of individual eFuses
WR_DIS.RD_DIS, EFUSE_BLK0, 0, 1, [] wr_dis of RD_DIS
WR_DIS.DIS_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_ICACHE
WR_DIS.DIS_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DCACHE
WR_DIS.DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_ICACHE
WR_DIS.DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_DCACHE
WR_DIS.DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_FORCE_DOWNLOAD
WR_DIS.DIS_USB, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_USB
WR_DIS.DIS_TWAI, EFUSE_BLK0, 2, 1, [WR_DIS.DIS_CAN] wr_dis of DIS_TWAI
WR_DIS.DIS_BOOT_REMAP, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_BOOT_REMAP
WR_DIS.SOFT_DIS_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of SOFT_DIS_JTAG
WR_DIS.HARD_DIS_JTAG, EFUSE_BLK0, 2, 1, [] wr_dis of HARD_DIS_JTAG
WR_DIS.DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 2, 1, [] wr_dis of DIS_DOWNLOAD_MANUAL_ENCRYPT
WR_DIS.VDD_SPI_XPD, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_XPD
WR_DIS.VDD_SPI_TIEH, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_TIEH
WR_DIS.VDD_SPI_FORCE, EFUSE_BLK0, 3, 1, [] wr_dis of VDD_SPI_FORCE
WR_DIS.WDT_DELAY_SEL, EFUSE_BLK0, 3, 1, [] wr_dis of WDT_DELAY_SEL
WR_DIS.SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 4, 1, [] wr_dis of SPI_BOOT_CRYPT_CNT
WR_DIS.SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 5, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE0
WR_DIS.SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 6, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE1
WR_DIS.SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 7, 1, [] wr_dis of SECURE_BOOT_KEY_REVOKE2
WR_DIS.KEY_PURPOSE_0, EFUSE_BLK0, 8, 1, [WR_DIS.KEY0_PURPOSE] wr_dis of KEY_PURPOSE_0
WR_DIS.KEY_PURPOSE_1, EFUSE_BLK0, 9, 1, [WR_DIS.KEY1_PURPOSE] wr_dis of KEY_PURPOSE_1
WR_DIS.KEY_PURPOSE_2, EFUSE_BLK0, 10, 1, [WR_DIS.KEY2_PURPOSE] wr_dis of KEY_PURPOSE_2
WR_DIS.KEY_PURPOSE_3, EFUSE_BLK0, 11, 1, [WR_DIS.KEY3_PURPOSE] wr_dis of KEY_PURPOSE_3
WR_DIS.KEY_PURPOSE_4, EFUSE_BLK0, 12, 1, [WR_DIS.KEY4_PURPOSE] wr_dis of KEY_PURPOSE_4
WR_DIS.KEY_PURPOSE_5, EFUSE_BLK0, 13, 1, [WR_DIS.KEY5_PURPOSE] wr_dis of KEY_PURPOSE_5
WR_DIS.SECURE_BOOT_EN, EFUSE_BLK0, 15, 1, [] wr_dis of SECURE_BOOT_EN
WR_DIS.SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 16, 1, [] wr_dis of SECURE_BOOT_AGGRESSIVE_REVOKE
WR_DIS.FLASH_TPUW, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TPUW
WR_DIS.DIS_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_DOWNLOAD_MODE
WR_DIS.DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_LEGACY_SPI_BOOT
WR_DIS.UART_PRINT_CHANNEL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CHANNEL
WR_DIS.DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 18, 1, [] wr_dis of DIS_USB_DOWNLOAD_MODE
WR_DIS.ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 18, 1, [] wr_dis of ENABLE_SECURITY_DOWNLOAD
WR_DIS.UART_PRINT_CONTROL, EFUSE_BLK0, 18, 1, [] wr_dis of UART_PRINT_CONTROL
WR_DIS.PIN_POWER_SELECTION, EFUSE_BLK0, 18, 1, [] wr_dis of PIN_POWER_SELECTION
WR_DIS.FLASH_TYPE, EFUSE_BLK0, 18, 1, [] wr_dis of FLASH_TYPE
WR_DIS.FORCE_SEND_RESUME, EFUSE_BLK0, 18, 1, [] wr_dis of FORCE_SEND_RESUME
WR_DIS.SECURE_VERSION, EFUSE_BLK0, 18, 1, [] wr_dis of SECURE_VERSION
WR_DIS.BLK1, EFUSE_BLK0, 20, 1, [] wr_dis of BLOCK1
WR_DIS.MAC, EFUSE_BLK0, 20, 1, [WR_DIS.MAC_FACTORY] wr_dis of MAC
WR_DIS.SPI_PAD_CONFIG_CLK, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CLK
WR_DIS.SPI_PAD_CONFIG_Q, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_Q
WR_DIS.SPI_PAD_CONFIG_D, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D
WR_DIS.SPI_PAD_CONFIG_CS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_CS
WR_DIS.SPI_PAD_CONFIG_HD, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_HD
WR_DIS.SPI_PAD_CONFIG_WP, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_WP
WR_DIS.SPI_PAD_CONFIG_DQS, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_DQS
WR_DIS.SPI_PAD_CONFIG_D4, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D4
WR_DIS.SPI_PAD_CONFIG_D5, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D5
WR_DIS.SPI_PAD_CONFIG_D6, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D6
WR_DIS.SPI_PAD_CONFIG_D7, EFUSE_BLK0, 20, 1, [] wr_dis of SPI_PAD_CONFIG_D7
WR_DIS.WAFER_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MAJOR
WR_DIS.WAFER_VERSION_MINOR_HI, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_HI
WR_DIS.FLASH_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of FLASH_VERSION
WR_DIS.BLK_VERSION_MAJOR, EFUSE_BLK0, 20, 1, [] wr_dis of BLK_VERSION_MAJOR
WR_DIS.PSRAM_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PSRAM_VERSION
WR_DIS.PKG_VERSION, EFUSE_BLK0, 20, 1, [] wr_dis of PKG_VERSION
WR_DIS.WAFER_VERSION_MINOR_LO, EFUSE_BLK0, 20, 1, [] wr_dis of WAFER_VERSION_MINOR_LO
WR_DIS.SYS_DATA_PART1, EFUSE_BLK0, 21, 1, [] wr_dis of BLOCK2
WR_DIS.OPTIONAL_UNIQUE_ID, EFUSE_BLK0, 21, 1, [] wr_dis of OPTIONAL_UNIQUE_ID
WR_DIS.ADC_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of ADC_CALIB
WR_DIS.BLK_VERSION_MINOR, EFUSE_BLK0, 21, 1, [] wr_dis of BLK_VERSION_MINOR
WR_DIS.TEMP_CALIB, EFUSE_BLK0, 21, 1, [] wr_dis of TEMP_CALIB
WR_DIS.RTCCALIB_V1IDX_A10H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A10H
WR_DIS.RTCCALIB_V1IDX_A11H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A11H
WR_DIS.RTCCALIB_V1IDX_A12H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A12H
WR_DIS.RTCCALIB_V1IDX_A13H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A13H
WR_DIS.RTCCALIB_V1IDX_A20H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A20H
WR_DIS.RTCCALIB_V1IDX_A21H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A21H
WR_DIS.RTCCALIB_V1IDX_A22H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A22H
WR_DIS.RTCCALIB_V1IDX_A23H, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A23H
WR_DIS.RTCCALIB_V1IDX_A10L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A10L
WR_DIS.RTCCALIB_V1IDX_A11L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A11L
WR_DIS.RTCCALIB_V1IDX_A12L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A12L
WR_DIS.RTCCALIB_V1IDX_A13L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A13L
WR_DIS.RTCCALIB_V1IDX_A20L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A20L
WR_DIS.RTCCALIB_V1IDX_A21L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A21L
WR_DIS.RTCCALIB_V1IDX_A22L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A22L
WR_DIS.RTCCALIB_V1IDX_A23L, EFUSE_BLK0, 21, 1, [] wr_dis of RTCCALIB_V1IDX_A23L
WR_DIS.BLOCK_USR_DATA, EFUSE_BLK0, 22, 1, [WR_DIS.USER_DATA] wr_dis of BLOCK_USR_DATA
WR_DIS.CUSTOM_MAC, EFUSE_BLK0, 22, 1, [WR_DIS.MAC_CUSTOM WR_DIS.USER_DATA_MAC_CUSTOM] wr_dis of CUSTOM_MAC
WR_DIS.BLOCK_KEY0, EFUSE_BLK0, 23, 1, [WR_DIS.KEY0] wr_dis of BLOCK_KEY0
WR_DIS.BLOCK_KEY1, EFUSE_BLK0, 24, 1, [WR_DIS.KEY1] wr_dis of BLOCK_KEY1
WR_DIS.BLOCK_KEY2, EFUSE_BLK0, 25, 1, [WR_DIS.KEY2] wr_dis of BLOCK_KEY2
WR_DIS.BLOCK_KEY3, EFUSE_BLK0, 26, 1, [WR_DIS.KEY3] wr_dis of BLOCK_KEY3
WR_DIS.BLOCK_KEY4, EFUSE_BLK0, 27, 1, [WR_DIS.KEY4] wr_dis of BLOCK_KEY4
WR_DIS.BLOCK_KEY5, EFUSE_BLK0, 28, 1, [WR_DIS.KEY5] wr_dis of BLOCK_KEY5
WR_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 29, 1, [WR_DIS.SYS_DATA_PART2] wr_dis of BLOCK_SYS_DATA2
WR_DIS.USB_EXCHG_PINS, EFUSE_BLK0, 30, 1, [] wr_dis of USB_EXCHG_PINS
WR_DIS.USB_EXT_PHY_ENABLE, EFUSE_BLK0, 30, 1, [WR_DIS.EXT_PHY_ENABLE] wr_dis of USB_EXT_PHY_ENABLE
WR_DIS.USB_FORCE_NOPERSIST, EFUSE_BLK0, 30, 1, [] wr_dis of USB_FORCE_NOPERSIST
WR_DIS.BLOCK0_VERSION, EFUSE_BLK0, 30, 1, [] wr_dis of BLOCK0_VERSION
RD_DIS, EFUSE_BLK0, 32, 7, [] Disable reading from BlOCK4-10
RD_DIS.BLOCK_KEY0, EFUSE_BLK0, 32, 1, [RD_DIS.KEY0] rd_dis of BLOCK_KEY0
RD_DIS.BLOCK_KEY1, EFUSE_BLK0, 33, 1, [RD_DIS.KEY1] rd_dis of BLOCK_KEY1
RD_DIS.BLOCK_KEY2, EFUSE_BLK0, 34, 1, [RD_DIS.KEY2] rd_dis of BLOCK_KEY2
RD_DIS.BLOCK_KEY3, EFUSE_BLK0, 35, 1, [RD_DIS.KEY3] rd_dis of BLOCK_KEY3
RD_DIS.BLOCK_KEY4, EFUSE_BLK0, 36, 1, [RD_DIS.KEY4] rd_dis of BLOCK_KEY4
RD_DIS.BLOCK_KEY5, EFUSE_BLK0, 37, 1, [RD_DIS.KEY5] rd_dis of BLOCK_KEY5
RD_DIS.BLOCK_SYS_DATA2, EFUSE_BLK0, 38, 1, [RD_DIS.SYS_DATA_PART2] rd_dis of BLOCK_SYS_DATA2
DIS_ICACHE, EFUSE_BLK0, 40, 1, [] Set this bit to disable Icache
DIS_DCACHE, EFUSE_BLK0, 41, 1, [] Set this bit to disable Dcache
DIS_DOWNLOAD_ICACHE, EFUSE_BLK0, 42, 1, [] Disables Icache when SoC is in Download mode
DIS_DOWNLOAD_DCACHE, EFUSE_BLK0, 43, 1, [] Disables Dcache when SoC is in Download mode
DIS_FORCE_DOWNLOAD, EFUSE_BLK0, 44, 1, [] Set this bit to disable the function that forces chip into download mode
DIS_USB, EFUSE_BLK0, 45, 1, [] Set this bit to disable USB OTG function
DIS_TWAI, EFUSE_BLK0, 46, 1, [DIS_CAN] Set this bit to disable the TWAI Controller function
DIS_BOOT_REMAP, EFUSE_BLK0, 47, 1, [] Disables capability to Remap RAM to ROM address space
SOFT_DIS_JTAG, EFUSE_BLK0, 49, 1, [] Software disables JTAG. When software disabled; JTAG can be activated temporarily by HMAC peripheral
HARD_DIS_JTAG, EFUSE_BLK0, 50, 1, [] Hardware disables JTAG permanently
DIS_DOWNLOAD_MANUAL_ENCRYPT, EFUSE_BLK0, 51, 1, [] Disables flash encryption when in download boot modes
USB_EXCHG_PINS, EFUSE_BLK0, 56, 1, [] Set this bit to exchange USB D+ and D- pins
USB_EXT_PHY_ENABLE, EFUSE_BLK0, 57, 1, [EXT_PHY_ENABLE] Set this bit to enable external USB PHY
USB_FORCE_NOPERSIST, EFUSE_BLK0, 58, 1, [] If set; forces USB BVALID to 1
BLOCK0_VERSION, EFUSE_BLK0, 59, 2, [] BLOCK0 efuse version
VDD_SPI_XPD, EFUSE_BLK0, 68, 1, [] If VDD_SPI_FORCE is 1; this value determines if the VDD_SPI regulator is powered on
VDD_SPI_TIEH, EFUSE_BLK0, 69, 1, [] If VDD_SPI_FORCE is 1; determines VDD_SPI voltage {0: "VDD_SPI connects to 1.8 V LDO"; 1: "VDD_SPI connects to VDD3P3_RTC_IO"}
VDD_SPI_FORCE, EFUSE_BLK0, 70, 1, [] Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TIEH to configure VDD_SPI LDO
WDT_DELAY_SEL, EFUSE_BLK0, 80, 2, [] RTC watchdog timeout threshold; in unit of slow clock cycle {0: "40000"; 1: "80000"; 2: "160000"; 3: "320000"}
SPI_BOOT_CRYPT_CNT, EFUSE_BLK0, 82, 3, [] Enables flash encryption when 1 or 3 bits are set and disabled otherwise {0: "Disable"; 1: "Enable"; 3: "Disable"; 7: "Enable"}
SECURE_BOOT_KEY_REVOKE0, EFUSE_BLK0, 85, 1, [] Revoke 1st secure boot key
SECURE_BOOT_KEY_REVOKE1, EFUSE_BLK0, 86, 1, [] Revoke 2nd secure boot key
SECURE_BOOT_KEY_REVOKE2, EFUSE_BLK0, 87, 1, [] Revoke 3rd secure boot key
KEY_PURPOSE_0, EFUSE_BLK0, 88, 4, [KEY0_PURPOSE] Purpose of KEY0
KEY_PURPOSE_1, EFUSE_BLK0, 92, 4, [KEY1_PURPOSE] Purpose of KEY1
KEY_PURPOSE_2, EFUSE_BLK0, 96, 4, [KEY2_PURPOSE] Purpose of KEY2
KEY_PURPOSE_3, EFUSE_BLK0, 100, 4, [KEY3_PURPOSE] Purpose of KEY3
KEY_PURPOSE_4, EFUSE_BLK0, 104, 4, [KEY4_PURPOSE] Purpose of KEY4
KEY_PURPOSE_5, EFUSE_BLK0, 108, 4, [KEY5_PURPOSE] Purpose of KEY5
SECURE_BOOT_EN, EFUSE_BLK0, 116, 1, [] Set this bit to enable secure boot
SECURE_BOOT_AGGRESSIVE_REVOKE, EFUSE_BLK0, 117, 1, [] Set this bit to enable aggressive secure boot key revocation mode
FLASH_TPUW, EFUSE_BLK0, 124, 4, [] Configures flash startup delay after SoC power-up; in unit of (ms/2). When the value is 15; delay is 7.5 ms
DIS_DOWNLOAD_MODE, EFUSE_BLK0, 128, 1, [] Set this bit to disable all download boot modes
DIS_LEGACY_SPI_BOOT, EFUSE_BLK0, 129, 1, [] Set this bit to disable Legacy SPI boot mode
UART_PRINT_CHANNEL, EFUSE_BLK0, 130, 1, [] Selects the default UART for printing boot messages {0: "UART0"; 1: "UART1"}
DIS_USB_DOWNLOAD_MODE, EFUSE_BLK0, 132, 1, [] Set this bit to disable use of USB OTG in UART download boot mode
ENABLE_SECURITY_DOWNLOAD, EFUSE_BLK0, 133, 1, [] Set this bit to enable secure UART download mode (read/write flash only)
UART_PRINT_CONTROL, EFUSE_BLK0, 134, 2, [] Set the default UART boot message output mode {0: "Enable"; 1: "Enable when GPIO46 is low at reset"; 2: "Enable when GPIO46 is high at reset"; 3: "Disable"}
PIN_POWER_SELECTION, EFUSE_BLK0, 136, 1, [] Set default power supply for GPIO33-GPIO37; set when SPI flash is initialized {0: "VDD3P3_CPU"; 1: "VDD_SPI"}
FLASH_TYPE, EFUSE_BLK0, 137, 1, [] SPI flash type {0: "4 data lines"; 1: "8 data lines"}
FORCE_SEND_RESUME, EFUSE_BLK0, 138, 1, [] If set; forces ROM code to send an SPI flash resume command during SPI boot
SECURE_VERSION, EFUSE_BLK0, 139, 16, [] Secure version (used by ESP-IDF anti-rollback feature)
DISABLE_WAFER_VERSION_MAJOR, EFUSE_BLK0, 160, 1, [] Disables check of wafer version major
DISABLE_BLK_VERSION_MAJOR, EFUSE_BLK0, 161, 1, [] Disables check of blk version major
MAC, EFUSE_BLK1, 40, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 32, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 24, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 16, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 8, 8, [MAC_FACTORY] MAC address
, EFUSE_BLK1, 0, 8, [MAC_FACTORY] MAC address
SPI_PAD_CONFIG_CLK, EFUSE_BLK1, 48, 6, [] SPI_PAD_configure CLK
SPI_PAD_CONFIG_Q, EFUSE_BLK1, 54, 6, [] SPI_PAD_configure Q(D1)
SPI_PAD_CONFIG_D, EFUSE_BLK1, 60, 6, [] SPI_PAD_configure D(D0)
SPI_PAD_CONFIG_CS, EFUSE_BLK1, 66, 6, [] SPI_PAD_configure CS
SPI_PAD_CONFIG_HD, EFUSE_BLK1, 72, 6, [] SPI_PAD_configure HD(D3)
SPI_PAD_CONFIG_WP, EFUSE_BLK1, 78, 6, [] SPI_PAD_configure WP(D2)
SPI_PAD_CONFIG_DQS, EFUSE_BLK1, 84, 6, [] SPI_PAD_configure DQS
SPI_PAD_CONFIG_D4, EFUSE_BLK1, 90, 6, [] SPI_PAD_configure D4
SPI_PAD_CONFIG_D5, EFUSE_BLK1, 96, 6, [] SPI_PAD_configure D5
SPI_PAD_CONFIG_D6, EFUSE_BLK1, 102, 6, [] SPI_PAD_configure D6
SPI_PAD_CONFIG_D7, EFUSE_BLK1, 108, 6, [] SPI_PAD_configure D7
WAFER_VERSION_MAJOR, EFUSE_BLK1, 114, 2, [] WAFER_VERSION_MAJOR
WAFER_VERSION_MINOR_HI, EFUSE_BLK1, 116, 1, [] WAFER_VERSION_MINOR most significant bit
FLASH_VERSION, EFUSE_BLK1, 117, 4, [] Flash version
BLK_VERSION_MAJOR, EFUSE_BLK1, 121, 2, [] BLK_VERSION_MAJOR
PSRAM_VERSION, EFUSE_BLK1, 124, 4, [] PSRAM version
PKG_VERSION, EFUSE_BLK1, 128, 4, [] Package version
WAFER_VERSION_MINOR_LO, EFUSE_BLK1, 132, 3, [] WAFER_VERSION_MINOR least significant bits
OPTIONAL_UNIQUE_ID, EFUSE_BLK2, 0, 128, [] Optional unique 128-bit ID
ADC_CALIB, EFUSE_BLK2, 128, 4, [] 4 bit of ADC calibration
BLK_VERSION_MINOR, EFUSE_BLK2, 132, 3, [] BLK_VERSION_MINOR of BLOCK2 {0: "No calib"; 1: "ADC calib V1"; 2: "ADC calib V2"}
TEMP_CALIB, EFUSE_BLK2, 135, 9, [] Temperature calibration data
RTCCALIB_V1IDX_A10H, EFUSE_BLK2, 144, 8, []
RTCCALIB_V1IDX_A11H, EFUSE_BLK2, 152, 8, []
RTCCALIB_V1IDX_A12H, EFUSE_BLK2, 160, 8, []
RTCCALIB_V1IDX_A13H, EFUSE_BLK2, 168, 8, []
RTCCALIB_V1IDX_A20H, EFUSE_BLK2, 176, 8, []
RTCCALIB_V1IDX_A21H, EFUSE_BLK2, 184, 8, []
RTCCALIB_V1IDX_A22H, EFUSE_BLK2, 192, 8, []
RTCCALIB_V1IDX_A23H, EFUSE_BLK2, 200, 8, []
RTCCALIB_V1IDX_A10L, EFUSE_BLK2, 208, 6, []
RTCCALIB_V1IDX_A11L, EFUSE_BLK2, 214, 6, []
RTCCALIB_V1IDX_A12L, EFUSE_BLK2, 220, 6, []
RTCCALIB_V1IDX_A13L, EFUSE_BLK2, 226, 6, []
RTCCALIB_V1IDX_A20L, EFUSE_BLK2, 232, 6, []
RTCCALIB_V1IDX_A21L, EFUSE_BLK2, 238, 6, []
RTCCALIB_V1IDX_A22L, EFUSE_BLK2, 244, 6, []
RTCCALIB_V1IDX_A23L, EFUSE_BLK2, 250, 6, []
USER_DATA, EFUSE_BLK3, 0, 256, [BLOCK_USR_DATA] User data
USER_DATA.MAC_CUSTOM, EFUSE_BLK3, 200, 48, [MAC_CUSTOM CUSTOM_MAC] Custom MAC
KEY0, EFUSE_BLK4, 0, 256, [BLOCK_KEY0] Key0 or user data
KEY1, EFUSE_BLK5, 0, 256, [BLOCK_KEY1] Key1 or user data
KEY2, EFUSE_BLK6, 0, 256, [BLOCK_KEY2] Key2 or user data
KEY3, EFUSE_BLK7, 0, 256, [BLOCK_KEY3] Key3 or user data
KEY4, EFUSE_BLK8, 0, 256, [BLOCK_KEY4] Key4 or user data
KEY5, EFUSE_BLK9, 0, 256, [BLOCK_KEY5] Key5 or user data
SYS_DATA_PART2, EFUSE_BLK10, 0, 256, [BLOCK_SYS_DATA2] System data part 2 (reserved)
Can't render this file because it contains an unexpected character in line 7 and column 87.

196
components/efuse/esp32s2/include/esp_efuse_table.h
View File

@@ -10,7 +10,7 @@ extern "C" {
#include "esp_efuse.h"
// md5_digest_table 10aa3ea5c0748be491a49b2b2d889166
// md5_digest_table 42c79ddff54c8f03645a832a69f60af2
// This file was generated from the file esp_efuse_table.csv. DO NOT CHANGE THIS FILE MANUALLY.
// If you want to change some fields, you need to change esp_efuse_table.csv file
// then run `efuse_common_table` or `efuse_custom_table` command it will generate this file.
@@ -19,56 +19,148 @@ extern "C" {
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_RTC_RAM_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DCACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_DCACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_FORCE_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_TWAI[];
#define ESP_EFUSE_WR_DIS_DIS_CAN ESP_EFUSE_WR_DIS_DIS_TWAI
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_BOOT_REMAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_HARD_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_XPD[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_TIEH[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_VDD_SPI_FORCE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WDT_DELAY_SEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_BOOT_CRYPT_CNT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_KEY_REVOKE2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5_PURPOSE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_0[];
#define ESP_EFUSE_WR_DIS_KEY0_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_0
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_1[];
#define ESP_EFUSE_WR_DIS_KEY1_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_1
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_2[];
#define ESP_EFUSE_WR_DIS_KEY2_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_3[];
#define ESP_EFUSE_WR_DIS_KEY3_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_3
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_4[];
#define ESP_EFUSE_WR_DIS_KEY4_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_4
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY_PURPOSE_5[];
#define ESP_EFUSE_WR_DIS_KEY5_PURPOSE ESP_EFUSE_WR_DIS_KEY_PURPOSE_5
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_BOOT_AGGRESSIVE_REVOKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_GROUP_3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TPUW[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_LEGACY_SPI_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CHANNEL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_DIS_USB_DOWNLOAD_MODE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ENABLE_SECURITY_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_UART_PRINT_CONTROL[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PIN_POWER_SELECTION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_TYPE[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_MAC[];
#define ESP_EFUSE_WR_DIS_MAC_FACTORY ESP_EFUSE_WR_DIS_MAC
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_Q[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_CS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_HD[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_WP[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_DQS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_HI[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_FLASH_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PSRAM_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_WAFER_VERSION_MINOR_LO[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USER_DATA[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY0[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY1[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY3[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY4[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_SYS_DATA_PART2[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_ADC_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10H[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11H[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12H[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13H[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20H[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21H[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22H[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23H[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A10L[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A11L[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A12L[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A13L[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A20L[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A21L[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A22L[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_RTCCALIB_V1IDX_A23L[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_USR_DATA[];
#define ESP_EFUSE_WR_DIS_USER_DATA ESP_EFUSE_WR_DIS_BLOCK_USR_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_CUSTOM_MAC[];
#define ESP_EFUSE_WR_DIS_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
#define ESP_EFUSE_WR_DIS_USER_DATA_MAC_CUSTOM ESP_EFUSE_WR_DIS_CUSTOM_MAC
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY0[];
#define ESP_EFUSE_WR_DIS_KEY0 ESP_EFUSE_WR_DIS_BLOCK_KEY0
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY1[];
#define ESP_EFUSE_WR_DIS_KEY1 ESP_EFUSE_WR_DIS_BLOCK_KEY1
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY2[];
#define ESP_EFUSE_WR_DIS_KEY2 ESP_EFUSE_WR_DIS_BLOCK_KEY2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY3[];
#define ESP_EFUSE_WR_DIS_KEY3 ESP_EFUSE_WR_DIS_BLOCK_KEY3
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY4[];
#define ESP_EFUSE_WR_DIS_KEY4 ESP_EFUSE_WR_DIS_BLOCK_KEY4
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_KEY5[];
#define ESP_EFUSE_WR_DIS_KEY5 ESP_EFUSE_WR_DIS_BLOCK_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_WR_DIS_SYS_DATA_PART2 ESP_EFUSE_WR_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE[];
#define ESP_EFUSE_WR_DIS_EXT_PHY_ENABLE ESP_EFUSE_WR_DIS_USB_EXT_PHY_ENABLE
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_USB_FORCE_NOPERSIST[];
extern const esp_efuse_desc_t* ESP_EFUSE_WR_DIS_BLOCK0_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY0[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY1[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY2[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY3[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY4[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_KEY5[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_SYS_DATA_PART2[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_RTC_RAM_BOOT[];
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY0[];
#define ESP_EFUSE_RD_DIS_KEY0 ESP_EFUSE_RD_DIS_BLOCK_KEY0
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY1[];
#define ESP_EFUSE_RD_DIS_KEY1 ESP_EFUSE_RD_DIS_BLOCK_KEY1
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY2[];
#define ESP_EFUSE_RD_DIS_KEY2 ESP_EFUSE_RD_DIS_BLOCK_KEY2
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY3[];
#define ESP_EFUSE_RD_DIS_KEY3 ESP_EFUSE_RD_DIS_BLOCK_KEY3
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY4[];
#define ESP_EFUSE_RD_DIS_KEY4 ESP_EFUSE_RD_DIS_BLOCK_KEY4
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_KEY5[];
#define ESP_EFUSE_RD_DIS_KEY5 ESP_EFUSE_RD_DIS_BLOCK_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2[];
#define ESP_EFUSE_RD_DIS_SYS_DATA_PART2 ESP_EFUSE_RD_DIS_BLOCK_SYS_DATA2
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DCACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_ICACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_DCACHE[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_FORCE_DOWNLOAD[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_USB[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_CAN[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_TWAI[];
#define ESP_EFUSE_DIS_CAN ESP_EFUSE_DIS_TWAI
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_BOOT_REMAP[];
extern const esp_efuse_desc_t* ESP_EFUSE_SOFT_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_HARD_DIS_JTAG[];
extern const esp_efuse_desc_t* ESP_EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXCHG_PINS[];
extern const esp_efuse_desc_t* ESP_EFUSE_USB_EXT_PHY_ENABLE[];
#define ESP_EFUSE_EXT_PHY_ENABLE ESP_EFUSE_USB_EXT_PHY_ENABLE
extern const esp_efuse_desc_t* ESP_EFUSE_USB_FORCE_NOPERSIST[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLOCK0_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_XPD[];
extern const esp_efuse_desc_t* ESP_EFUSE_VDD_SPI_TIEH[];
@@ -79,11 +171,17 @@ extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE0[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE1[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_KEY_REVOKE2[];
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_0[];
#define ESP_EFUSE_KEY0_PURPOSE ESP_EFUSE_KEY_PURPOSE_0
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_1[];
#define ESP_EFUSE_KEY1_PURPOSE ESP_EFUSE_KEY_PURPOSE_1
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_2[];
#define ESP_EFUSE_KEY2_PURPOSE ESP_EFUSE_KEY_PURPOSE_2
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_3[];
#define ESP_EFUSE_KEY3_PURPOSE ESP_EFUSE_KEY_PURPOSE_3
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_4[];
#define ESP_EFUSE_KEY4_PURPOSE ESP_EFUSE_KEY_PURPOSE_4
extern const esp_efuse_desc_t* ESP_EFUSE_KEY_PURPOSE_5[];
#define ESP_EFUSE_KEY5_PURPOSE ESP_EFUSE_KEY_PURPOSE_5
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_EN[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_TPUW[];
@@ -99,35 +197,65 @@ extern const esp_efuse_desc_t* ESP_EFUSE_FORCE_SEND_RESUME[];
extern const esp_efuse_desc_t* ESP_EFUSE_SECURE_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_DISABLE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC_FACTORY[];
extern const esp_efuse_desc_t* ESP_EFUSE_MAC[];
#define ESP_EFUSE_MAC_FACTORY ESP_EFUSE_MAC
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CLK[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q_D1[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D_D0[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_Q[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_CS[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD_D3[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP_D2[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_HD[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_WP[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_DQS[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D4[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D5[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D6[];
extern const esp_efuse_desc_t* ESP_EFUSE_SPI_PAD_CONFIG_D7[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_HI[];
extern const esp_efuse_desc_t* ESP_EFUSE_FLASH_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MAJOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_PSRAM_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_PKG_VERSION[];
extern const esp_efuse_desc_t* ESP_EFUSE_WAFER_VERSION_MINOR_LO[];
extern const esp_efuse_desc_t* ESP_EFUSE_OPTIONAL_UNIQUE_ID[];
extern const esp_efuse_desc_t* ESP_EFUSE_ADC_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_BLK_VERSION_MINOR[];
extern const esp_efuse_desc_t* ESP_EFUSE_TEMP_CALIB[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10H[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11H[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12H[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13H[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20H[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21H[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22H[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23H[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A10L[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A11L[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A12L[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A13L[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A20L[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A21L[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A22L[];
extern const esp_efuse_desc_t* ESP_EFUSE_RTCCALIB_V1IDX_A23L[];
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA[];
#define ESP_EFUSE_BLOCK_USR_DATA ESP_EFUSE_USER_DATA
extern const esp_efuse_desc_t* ESP_EFUSE_USER_DATA_MAC_CUSTOM[];
#define ESP_EFUSE_MAC_CUSTOM ESP_EFUSE_USER_DATA_MAC_CUSTOM
#define ESP_EFUSE_CUSTOM_MAC ESP_EFUSE_USER_DATA_MAC_CUSTOM
extern const esp_efuse_desc_t* ESP_EFUSE_KEY0[];
#define ESP_EFUSE_BLOCK_KEY0 ESP_EFUSE_KEY0
extern const esp_efuse_desc_t* ESP_EFUSE_KEY1[];
#define ESP_EFUSE_BLOCK_KEY1 ESP_EFUSE_KEY1
extern const esp_efuse_desc_t* ESP_EFUSE_KEY2[];
#define ESP_EFUSE_BLOCK_KEY2 ESP_EFUSE_KEY2
extern const esp_efuse_desc_t* ESP_EFUSE_KEY3[];
#define ESP_EFUSE_BLOCK_KEY3 ESP_EFUSE_KEY3
extern const esp_efuse_desc_t* ESP_EFUSE_KEY4[];
#define ESP_EFUSE_BLOCK_KEY4 ESP_EFUSE_KEY4
extern const esp_efuse_desc_t* ESP_EFUSE_KEY5[];
#define ESP_EFUSE_BLOCK_KEY5 ESP_EFUSE_KEY5
extern const esp_efuse_desc_t* ESP_EFUSE_SYS_DATA_PART2[];
#define ESP_EFUSE_BLOCK_SYS_DATA2 ESP_EFUSE_SYS_DATA_PART2
#ifdef __cplusplus
}