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feat(clock): support apll clock on p4

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laokaiyao
2024-08-27 09:44:27 +08:00
committed by Kevin (Lao Kaiyao)
parent 9f4b1bd471
commit 5b03fff32e
7 changed files with 307 additions and 9 deletions
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84
components/hal/esp32p4/include/hal/clk_tree_ll.h
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@@ -17,6 +17,7 @@
#include "soc/pmu_reg.h"
#include "hal/regi2c_ctrl.h"
#include "soc/regi2c_cpll.h"
#include "soc/regi2c_apll.h"
#include "soc/regi2c_mpll.h"
#include "soc/regi2c_bias.h"
#include "hal/assert.h"
@@ -45,8 +46,17 @@ extern "C" {
#define CLK_LL_PLL_480M_FREQ_MHZ (480)
#define CLK_LL_PLL_500M_FREQ_MHZ (500)
/* APLL configuration parameters */
#define CLK_LL_APLL_SDM_STOP_VAL_1 0x09
#define CLK_LL_APLL_SDM_STOP_VAL_2_REV0 0x69
#define CLK_LL_APLL_SDM_STOP_VAL_2_REV1 0x49
/* APLL calibration parameters */
#define CLK_LL_APLL_CAL_DELAY_1 0x0f
#define CLK_LL_APLL_CAL_DELAY_2 0x3f
#define CLK_LL_APLL_CAL_DELAY_3 0x1f
/* APLL multiplier output frequency range */
// TODO: IDF-8884 check if the APLL frequency range is same as before
// apll_multiplier_out = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)
#define CLK_LL_APLL_MULTIPLIER_MIN_HZ (350000000) // 350 MHz
#define CLK_LL_APLL_MULTIPLIER_MAX_HZ (500000000) // 500 MHz
@@ -99,6 +109,24 @@ static inline __attribute__((always_inline)) void clk_ll_cpll_disable(void)
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_CPLL | PMU_TIE_LOW_XPD_CPLL_I2C);
}
/**
* @brief Power up APLL circuit
*/
static inline __attribute__((always_inline)) void clk_ll_apll_enable(void)
{
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_XPD_APLL | PMU_TIE_HIGH_XPD_APLL_I2C);
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_HIGH_GLOBAL_APLL_ICG);
}
/**
* @brief Power down APLL circuit
*/
static inline __attribute__((always_inline)) void clk_ll_apll_disable(void)
{
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_GLOBAL_APLL_ICG) ;
SET_PERI_REG_MASK(PMU_IMM_HP_CK_POWER_REG, PMU_TIE_LOW_XPD_APLL | PMU_TIE_LOW_XPD_APLL_I2C);
}
/**
* @brief Enable the internal oscillator output for LP_PLL_CLK
*/
@@ -424,6 +452,60 @@ static inline __attribute__((always_inline)) void clk_ll_mpll_set_config(uint32_
REGI2C_WRITE(I2C_MPLL, I2C_MPLL_DIV_REG_ADDR, val);
}
/**
* @brief Get APLL configuration which can be used to calculate APLL frequency
*
* @param[out] o_div Frequency divider, 0..31
* @param[out] sdm0 Frequency adjustment parameter, 0..255
* @param[out] sdm1 Frequency adjustment parameter, 0..255
* @param[out] sdm2 Frequency adjustment parameter, 0..63
*/
static inline __attribute__((always_inline)) void clk_ll_apll_get_config(uint32_t *o_div, uint32_t *sdm0, uint32_t *sdm1, uint32_t *sdm2)
{
*o_div = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV);
*sdm0 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM0);
*sdm1 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM1);
*sdm2 = REGI2C_READ_MASK(I2C_APLL, I2C_APLL_DSDM2);
}
/**
* @brief Set APLL configuration
*
* @param o_div Frequency divider, 0..31
* @param sdm0 Frequency adjustment parameter, 0..255
* @param sdm1 Frequency adjustment parameter, 0..255
* @param sdm2 Frequency adjustment parameter, 0..63
*/
static inline __attribute__((always_inline)) void clk_ll_apll_set_config(uint32_t o_div, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2)
{
REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM2, sdm2);
REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM0, sdm0);
REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_DSDM1, sdm1);
REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, CLK_LL_APLL_SDM_STOP_VAL_1);
REGI2C_WRITE(I2C_APLL, I2C_APLL_SDM_STOP, CLK_LL_APLL_SDM_STOP_VAL_2_REV1);
REGI2C_WRITE_MASK(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
}
/**
* @brief Set APLL calibration parameters
*/
static inline __attribute__((always_inline)) void clk_ll_apll_set_calibration(void)
{
REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_1);
REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_2);
REGI2C_WRITE(I2C_APLL, I2C_APLL_IR_CAL_DELAY, CLK_LL_APLL_CAL_DELAY_3);
}
/**
* @brief Check whether APLL calibration is done
*
* @return True if calibration is done; otherwise false
*/
static inline __attribute__((always_inline)) bool clk_ll_apll_calibration_is_done(void)
{
return REGI2C_READ_MASK(I2C_APLL, I2C_APLL_OR_CAL_END);
}
/**
* @brief To enable the change of cpu_div_num, mem_div_num, sys_div_num, and apb_div_num
*/