feat(clock): support apll clock on p4

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -767,6 +767,10 @@ config SOC_I2S_SUPPORTS_XTAL
     bool
     default y
 
+config SOC_I2S_SUPPORTS_APLL
+    bool
+    default y
+
 config SOC_I2S_SUPPORTS_PCM
     bool
     default y
@@ -1695,6 +1699,10 @@ config SOC_MODEM_CLOCK_IS_INDEPENDENT
     bool
     default n
 
+config SOC_CLK_APLL_SUPPORTED
+    bool
+    default y
+
 config SOC_CLK_MPLL_SUPPORTED
     bool
     default y

components/soc/esp32p4/include/soc/regi2c_apll.h

@@ -0,0 +1,127 @@
+/*
+ * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#pragma once
+
+/**
+ * @file regi2c_apll.h
+ * @brief Register definitions for audio PLL (APLL)
+ *
+ * This file lists register fields of APLL, located on an internal configuration
+ * bus. These definitions are used via macros defined in regi2c_ctrl.h, by
+ * rtc_clk_apll_freq_set and rtc_clk_apll_enable function in rtc_clk.c.
+ */
+
+#define I2C_APLL            0X6F
+#define I2C_APLL_HOSTID     1
+
+#define I2C_APLL_IR_CAL_DELAY        0
+#define I2C_APLL_IR_CAL_DELAY_MSB    3
+#define I2C_APLL_IR_CAL_DELAY_LSB    0
+
+#define I2C_APLL_IR_CAL_RSTB        0
+#define I2C_APLL_IR_CAL_RSTB_MSB    4
+#define I2C_APLL_IR_CAL_RSTB_LSB    4
+
+#define I2C_APLL_IR_CAL_START        0
+#define I2C_APLL_IR_CAL_START_MSB    5
+#define I2C_APLL_IR_CAL_START_LSB    5
+
+#define I2C_APLL_IR_CAL_UNSTOP        0
+#define I2C_APLL_IR_CAL_UNSTOP_MSB    6
+#define I2C_APLL_IR_CAL_UNSTOP_LSB    6
+
+#define I2C_APLL_OC_ENB_FCAL        0
+#define I2C_APLL_OC_ENB_FCAL_MSB    7
+#define I2C_APLL_OC_ENB_FCAL_LSB    7
+
+#define I2C_APLL_IR_CAL_EXT_CAP        1
+#define I2C_APLL_IR_CAL_EXT_CAP_MSB    4
+#define I2C_APLL_IR_CAL_EXT_CAP_LSB    0
+
+#define I2C_APLL_IR_CAL_ENX_CAP        1
+#define I2C_APLL_IR_CAL_ENX_CAP_MSB    5
+#define I2C_APLL_IR_CAL_ENX_CAP_LSB    5
+
+#define I2C_APLL_OC_LBW        1
+#define I2C_APLL_OC_LBW_MSB    6
+#define I2C_APLL_OC_LBW_LSB    6
+
+#define I2C_APLL_IR_CAL_CK_DIV        2
+#define I2C_APLL_IR_CAL_CK_DIV_MSB    3
+#define I2C_APLL_IR_CAL_CK_DIV_LSB    0
+
+#define I2C_APLL_OC_DCHGP        2
+#define I2C_APLL_OC_DCHGP_MSB    6
+#define I2C_APLL_OC_DCHGP_LSB    4
+
+#define I2C_APLL_OC_ENB_VCON        2
+#define I2C_APLL_OC_ENB_VCON_MSB    7
+#define I2C_APLL_OC_ENB_VCON_LSB    7
+
+#define I2C_APLL_OR_CAL_CAP        3
+#define I2C_APLL_OR_CAL_CAP_MSB    4
+#define I2C_APLL_OR_CAL_CAP_LSB    0
+
+#define I2C_APLL_OR_CAL_UDF        3
+#define I2C_APLL_OR_CAL_UDF_MSB    5
+#define I2C_APLL_OR_CAL_UDF_LSB    5
+
+#define I2C_APLL_OR_CAL_OVF        3
+#define I2C_APLL_OR_CAL_OVF_MSB    6
+#define I2C_APLL_OR_CAL_OVF_LSB    6
+
+#define I2C_APLL_OR_CAL_END        3
+#define I2C_APLL_OR_CAL_END_MSB    7
+#define I2C_APLL_OR_CAL_END_LSB    7
+
+#define I2C_APLL_OR_OUTPUT_DIV        4
+#define I2C_APLL_OR_OUTPUT_DIV_MSB    4
+#define I2C_APLL_OR_OUTPUT_DIV_LSB    0
+
+#define I2C_APLL_OC_TSCHGP        4
+#define I2C_APLL_OC_TSCHGP_MSB    6
+#define I2C_APLL_OC_TSCHGP_LSB    6
+
+#define I2C_APLL_EN_FAST_CAL        4
+#define I2C_APLL_EN_FAST_CAL_MSB    7
+#define I2C_APLL_EN_FAST_CAL_LSB    7
+
+#define I2C_APLL_OC_DHREF_SEL        5
+#define I2C_APLL_OC_DHREF_SEL_MSB    1
+#define I2C_APLL_OC_DHREF_SEL_LSB    0
+
+#define I2C_APLL_OC_DLREF_SEL        5
+#define I2C_APLL_OC_DLREF_SEL_MSB    3
+#define I2C_APLL_OC_DLREF_SEL_LSB    2
+
+#define I2C_APLL_SDM_DITHER        5
+#define I2C_APLL_SDM_DITHER_MSB    4
+#define I2C_APLL_SDM_DITHER_LSB    4
+
+#define I2C_APLL_SDM_STOP        5
+#define I2C_APLL_SDM_STOP_MSB    5
+#define I2C_APLL_SDM_STOP_LSB    5
+
+#define I2C_APLL_SDM_RSTB        5
+#define I2C_APLL_SDM_RSTB_MSB    6
+#define I2C_APLL_SDM_RSTB_LSB    6
+
+#define I2C_APLL_OC_DVDD        6
+#define I2C_APLL_OC_DVDD_MSB    4
+#define I2C_APLL_OC_DVDD_LSB    0
+
+#define I2C_APLL_DSDM2        7
+#define I2C_APLL_DSDM2_MSB    5
+#define I2C_APLL_DSDM2_LSB    0
+
+#define I2C_APLL_DSDM1        8
+#define I2C_APLL_DSDM1_MSB    7
+#define I2C_APLL_DSDM1_LSB    0
+
+#define I2C_APLL_DSDM0        9
+#define I2C_APLL_DSDM0_MSB    7
+#define I2C_APLL_DSDM0_LSB    0

components/soc/esp32p4/include/soc/soc_caps.h

@@ -309,7 +309,7 @@
 #define SOC_I2S_NUM                 (3U)
 #define SOC_I2S_HW_VERSION_2        (1)
 #define SOC_I2S_SUPPORTS_XTAL       (1)
-// #define SOC_I2S_SUPPORTS_APLL       (1) // TODO: IDF-8884
+#define SOC_I2S_SUPPORTS_APLL       (1)
 #define SOC_I2S_SUPPORTS_PCM        (1)
 #define SOC_I2S_SUPPORTS_PDM        (1)
 #define SOC_I2S_SUPPORTS_PDM_TX     (1)
@@ -664,7 +664,7 @@
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
 #define SOC_MODEM_CLOCK_IS_INDEPENDENT            (0)
 
-// #define SOC_CLK_APLL_SUPPORTED                    (1)     /*!< Support Audio PLL */ TODO: IDF-8884
+#define SOC_CLK_APLL_SUPPORTED                    (1)     /*!< Support Audio PLL */
 #define SOC_CLK_MPLL_SUPPORTED                    (1)     /*!< Support MSPI PLL */
 #define SOC_CLK_XTAL32K_SUPPORTED                 (1)     /*!< Support to connect an external low frequency crystal */
 #define SOC_CLK_RC32K_SUPPORTED                   (1)     /*!< Support an internal 32kHz RC oscillator */