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fix(gpio): fix 8/16-bit gpio, rtc/lp_io register access

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This commit is contained in:
Song Ruo Jing
2024-12-20 21:14:34 +08:00
parent 3fde2017cd
commit 5b75572f23
17 changed files with 73 additions and 59 deletions
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7
components/hal/esp32h2/include/hal/gpio_ll.h
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@@ -81,7 +81,7 @@ static inline void gpio_ll_get_io_config(gpio_dev_t *hw, uint32_t gpio_num,
*fun_sel = (iomux_reg_val & MCU_SEL_M) >> MCU_SEL_S;
}
if (sig_out) {
*sig_out = hw->func_out_sel_cfg[gpio_num].out_sel;
*sig_out = HAL_FORCE_READ_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel);
}
if (slp_sel) {
*slp_sel = (iomux_reg_val & SLP_SEL_M) >> SLP_SEL_S;
@@ -378,10 +378,7 @@ static inline void gpio_ll_od_enable(gpio_dev_t *hw, gpio_num_t gpio_num)
__attribute__((always_inline))
static inline void gpio_ll_matrix_out_default(gpio_dev_t *hw, uint32_t gpio_num)
{
gpio_func_out_sel_cfg_reg_t reg = {
.out_sel = SIG_GPIO_OUT_IDX,
};
hw->func_out_sel_cfg[gpio_num].val = reg.val;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->func_out_sel_cfg[gpio_num], out_sel, SIG_GPIO_OUT_IDX);
}
/**