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Merge branch 'feature/modify_mcpwm_clock_pre_scale_v5.1' into 'release/v5.1'
feat(mcpwm): Make the MCPWM capture timer's resolution configurable (v5.1) See merge request espressif/esp-idf!25904
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@@ -45,10 +45,12 @@ extern "C" {
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#define MCPWM_LL_EVENT_CAPTURE(cap) (1 << ((cap) + 27))
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// Maximum values due to limited register bit width
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#define MCPWM_LL_MAX_GROUP_PRESCALE 256
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#define MCPWM_LL_MAX_TIMER_PRESCALE 256
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#define MCPWM_LL_MAX_CARRIER_PRESCALE 16
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#define MCPWM_LL_MAX_CARRIER_ONESHOT 16
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#define MCPWM_LL_MAX_CAPTURE_PRESCALE 256
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#define MCPWM_LL_MAX_CAPTURE_TIMER_PRESCALE 1
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#define MCPWM_LL_MAX_DEAD_DELAY 65536
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#define MCPWM_LL_MAX_COUNT_VALUE 65536
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@@ -105,13 +107,14 @@ static inline void mcpwm_ll_group_enable_clock(mcpwm_dev_t *mcpwm, bool en)
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* @brief Set the MCPWM group clock prescale
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*
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* @param mcpwm Peripheral instance address
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* @param pre_scale Prescale value
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* @param prescale Prescale value
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*/
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static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int pre_scale)
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static inline void mcpwm_ll_group_set_clock_prescale(mcpwm_dev_t *mcpwm, int prescale)
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{
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(void)mcpwm; // only one MCPWM instance
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// group clock: PWM_clk = source_clock / (prescale + 1)
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.pwm_clk_conf, pwm_div_num, pre_scale - 1);
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// group clock: PWM_clk = source_clock / (prescale)
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HAL_ASSERT(prescale <= 256 && prescale > 0);
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.pwm_clk_conf, pwm_div_num, prescale - 1);
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}
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/**
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