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adc: improve power logic

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This commit is contained in:
Armando
2023-01-09 17:10:04 +08:00
parent f9da48d94f
commit 5be3c21cfc
28 changed files with 480 additions and 249 deletions
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25
components/hal/esp32/include/hal/adc_ll.h
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@@ -29,13 +29,6 @@ extern "C" {
#define ADC_LL_DEFAULT_CONV_LIMIT_EN 1
#define ADC_LL_DEFAULT_CONV_LIMIT_NUM 10
typedef enum {
ADC_POWER_BY_FSM, /*!< ADC XPD controlled by FSM. Used for polling mode */
ADC_POWER_SW_ON, /*!< ADC XPD controlled by SW. power on. Used for DMA mode */
ADC_POWER_SW_OFF, /*!< ADC XPD controlled by SW. power off. */
ADC_POWER_MAX, /*!< For parameter check. */
} adc_ll_power_t;
typedef enum {
ADC_RTC_DATA_OK = 0,
} adc_ll_rtc_raw_data_t;
@@ -553,24 +546,6 @@ static inline void adc_oneshot_ll_disable_all_unit(void)
/*---------------------------------------------------------------
Common setting
---------------------------------------------------------------*/
/**
* Set ADC module power management.
*
* @param manage Set ADC power status.
*/
static inline void adc_ll_set_power_manage(adc_ll_power_t manage)
{
/* Bit1 0:Fsm 1: SW mode
Bit0 0:SW mode power down 1: SW mode power on */
if (manage == ADC_POWER_SW_ON) {
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PU;
} else if (manage == ADC_POWER_BY_FSM) {
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_FSM;
} else if (manage == ADC_POWER_SW_OFF) {
SENS.sar_meas_wait2.force_xpd_sar = SENS_FORCE_XPD_SAR_PD;
}
}
/**
* Set ADC module controller.
* There are five SAR ADC controllers: