alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-09-30 19:19:21 +00:00
Code Issues Packages Projects Releases Wiki Activity

fix(hal): integer overflow found by coverity

Browse Source 
actually these "bugs" are harmless from the perspective of the hardware
This commit is contained in:
morris
2024-11-26 11:24:50 +08:00
parent 64960f0751
commit 5cae5090c2
30 changed files with 591 additions and 458 deletions
Download Patch File Download Diff File Expand all files Collapse all files

40
components/hal/esp32s2/include/hal/gpspi_flash_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -174,7 +174,7 @@ static inline bool gpspi_flash_ll_host_idle(const spi_dev_t *dev)
*/
static inline void gpspi_flash_ll_read_phase(spi_dev_t *dev)
{
typeof (dev->user) user = {
typeof(dev->user) user = {
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
@@ -209,9 +209,9 @@ static inline void gpspi_flash_ll_set_cs_pin(spi_dev_t *dev, int pin)
*/
static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl;
typeof(dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
typeof (dev->user) user;
typeof(dev->user) user;
user.val = dev->user.val;
ctrl.val &= ~(SPI_FCMD_QUAD_M | SPI_FADDR_QUAD_M | SPI_FREAD_QUAD_M | SPI_FCMD_DUAL_M | SPI_FADDR_DUAL_M | SPI_FREAD_DUAL_M);
@@ -219,7 +219,7 @@ static inline void gpspi_flash_ll_set_read_mode(spi_dev_t *dev, esp_flash_io_mod
switch (read_mode) {
case SPI_FLASH_FASTRD:
//the default option
//the default option
case SPI_FLASH_SLOWRD:
break;
case SPI_FLASH_QIO:
@@ -333,7 +333,7 @@ static inline void gpspi_flash_ll_set_addr_bitlen(spi_dev_t *dev, uint32_t bitle
static inline void gpspi_flash_ll_set_usr_address(spi_dev_t *dev, uint32_t addr, uint32_t bitlen)
{
// The blank region should be all ones
uint32_t padding_ones = (bitlen == 32? 0 : UINT32_MAX >> bitlen);
uint32_t padding_ones = (bitlen == 32 ? 0 : UINT32_MAX >> bitlen);
dev->addr = (addr << (32 - bitlen)) | padding_ones;
}
@@ -357,7 +357,9 @@ static inline void gpspi_flash_ll_set_address(spi_dev_t *dev, uint32_t addr)
static inline void gpspi_flash_ll_set_dummy(spi_dev_t *dev, uint32_t dummy_n)
{
dev->user.usr_dummy = dummy_n ? 1 : 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
if (dummy_n > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
}
}
/**
@@ -374,16 +376,32 @@ static inline void gpspi_flash_ll_set_dummy_out(spi_dev_t *dev, uint32_t out_en,
dev->ctrl.d_pol = out_lev;
}
/**
* Set extra hold time of CS after the clocks.
*
* @param dev Beginning address of the peripheral registers.
* @param hold_n Cycles of clocks before CS is inactive
*/
static inline void gpspi_flash_ll_set_hold(spi_dev_t *dev, uint32_t hold_n)
{
dev->ctrl2.cs_hold_time = hold_n - 1;
dev->user.cs_hold = (hold_n > 0? 1: 0);
dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
if (hold_n > 0) {
dev->ctrl2.cs_hold_time = hold_n - 1;
}
}
/**
* Set the delay of SPI clocks before the first SPI clock after the CS active edge.
*
* @param dev Beginning address of the peripheral registers.
* @param cs_setup_time Delay of SPI clocks after the CS active edge, 0 to disable the setup phase.
*/
static inline void gpspi_flash_ll_set_cs_setup(spi_dev_t *dev, uint32_t cs_setup_time)
{
dev->user.cs_setup = (cs_setup_time > 0 ? 1 : 0);
dev->ctrl2.cs_setup_time = cs_setup_time - 1;
if (cs_setup_time > 0) {
dev->ctrl2.cs_setup_time = cs_setup_time - 1;
}
}
/**
@@ -400,7 +418,7 @@ static inline uint32_t gpspi_flash_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv/2 - 1) & 0xff) << 6 ) | (((clkdiv - 1) & 0xff) << 12));
div_parameter = ((clkdiv - 1) | (((clkdiv / 2 - 1) & 0xff) << 6) | (((clkdiv - 1) & 0xff) << 12));
}
return div_parameter;
}

76
components/hal/esp32s2/include/hal/spi_ll.h
View File

@@ -90,7 +90,7 @@ typedef enum {
// SPI base command in esp32s2
typedef enum {
/* Slave HD Only */
/* Slave HD Only */
SPI_LL_BASE_CMD_HD_WRBUF = 0x01,
SPI_LL_BASE_CMD_HD_RDBUF = 0x02,
SPI_LL_BASE_CMD_HD_WRDMA = 0x03,
@@ -112,10 +112,10 @@ typedef enum {
* @param host_id Peripheral index number, see `spi_host_device_t`
* @param enable Enable/Disable
*/
static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
{
if (enable) {
switch (host_id)
{
switch (host_id) {
case SPI1_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
break;
@@ -128,8 +128,7 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
default: HAL_ASSERT(false);
}
} else {
switch (host_id)
{
switch (host_id) {
case SPI1_HOST:
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI01_CLK_EN);
break;
@@ -153,9 +152,9 @@ static inline void spi_ll_enable_bus_clock(spi_host_device_t host_id, bool enabl
*
* @param host_id Peripheral index number, see `spi_host_device_t`
*/
static inline void spi_ll_reset_register(spi_host_device_t host_id) {
switch (host_id)
{
static inline void spi_ll_reset_register(spi_host_device_t host_id)
{
switch (host_id) {
case SPI1_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI01_RST);
@@ -853,7 +852,9 @@ static inline void spi_ll_set_miso_delay(spi_dev_t *hw, int delay_mode, int dela
static inline void spi_ll_set_dummy(spi_dev_t *hw, int dummy_n)
{
hw->user.usr_dummy = dummy_n ? 1 : 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
if (dummy_n > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->user1, usr_dummy_cyclelen, dummy_n - 1);
}
}
/**
@@ -1207,10 +1208,10 @@ static inline uint32_t spi_ll_slave_hd_get_last_addr(spi_dev_t *hw)
* @param host_id Peripheral index number, see `spi_host_device_t`
* @param enable Enable/Disable
*/
static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable) {
static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool enable)
{
if (enable) {
switch (host_id)
{
switch (host_id) {
case SPI2_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_DMA_CLK_EN);
break;
@@ -1221,8 +1222,7 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e
HAL_ASSERT(false);
}
} else {
switch (host_id)
{
switch (host_id) {
case SPI2_HOST:
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI2_DMA_CLK_EN);
break;
@@ -1244,9 +1244,9 @@ static inline void spi_dma_ll_enable_bus_clock(spi_host_device_t host_id, bool e
*
* @param host_id Peripheral index number, see `spi_host_device_t`
*/
static inline void spi_dma_ll_reset_register(spi_host_device_t host_id) {
switch (host_id)
{
static inline void spi_dma_ll_reset_register(spi_host_device_t host_id)
{
switch (host_id) {
case SPI2_HOST:
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_DMA_RST);
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI2_DMA_RST);
@@ -1531,7 +1531,7 @@ static inline bool spi_ll_tx_get_empty_err(spi_dev_t *hw)
static inline void spi_ll_set_conf_base_bitslen(spi_dev_t *hw, uint8_t conf_base)
{
// 7 bits wide
if(conf_base < 128) {
if (conf_base < 128) {
hw->slv_wrbuf_dlen.conf_base_bitlen = conf_base;
}
}
@@ -1592,33 +1592,30 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod
conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_CTRL_MASK;
conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET] &= ~SPI_LL_ONE_LINE_USER_MASK;
switch (line_mode.cmd_lines)
{
switch (line_mode.cmd_lines) {
case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_DUAL_M); break;
case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_QUAD_M); break;
case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M ); break;
case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FCMD_OCT_M); break;
default: break;
}
switch (line_mode.addr_lines)
{
switch (line_mode.addr_lines) {
case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_DUAL_M); break;
case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_QUAD_M); break;
case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M ); break;
case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FADDR_OCT_M); break;
default: break;
}
switch (line_mode.data_lines)
{
case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M );
SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M);
break;
case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M );
SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M);
break;
case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_OCT_M );
SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_OCT_M);
break;
switch (line_mode.data_lines) {
case 2: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_DUAL_M);
SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_DUAL_M);
break;
case 4: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_QUAD_M);
SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_QUAD_M);
break;
case 8: SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_CTRL_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FREAD_OCT_M);
SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_FWRITE_OCT_M);
break;
default: break;
}
}
@@ -1633,7 +1630,7 @@ static inline void spi_ll_format_line_mode_conf_buff(spi_dev_t *hw, spi_line_mod
static inline void spi_ll_format_prep_phase_conf_buffer(spi_dev_t *hw, uint8_t setup, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX])
{
//user reg: cs_setup
if(setup) {
if (setup) {
SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M);
} else {
SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_SETUP_M);
@@ -1771,7 +1768,7 @@ static inline void spi_ll_format_din_phase_conf_buffer(spi_dev_t *hw, int bitlen
static inline void spi_ll_format_done_phase_conf_buffer(spi_dev_t *hw, int hold, uint32_t conf_buffer[SOC_SPI_SCT_BUFFER_NUM_MAX])
{
//user reg: cs_hold
if(hold) {
if (hold) {
SPI_LL_CONF_BUF_SET_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M);
} else {
SPI_LL_CONF_BUF_CLR_BIT(conf_buffer[SPI_LL_USER_REG_POS + SPI_LL_CONF_BUFFER_OFFSET], SPI_CS_HOLD_M);
@@ -1856,8 +1853,7 @@ static inline void spi_ll_set_magic_number(spi_dev_t *hw, uint8_t magic_value)
static inline uint8_t spi_ll_get_slave_hd_base_command(spi_command_t cmd_t)
{
uint8_t cmd_base = 0x00;
switch (cmd_t)
{
switch (cmd_t) {
case SPI_CMD_HD_WRBUF:
cmd_base = SPI_LL_BASE_CMD_HD_WRBUF;
break;

34
components/hal/esp32s2/include/hal/spimem_flash_ll.h
View File

@@ -353,7 +353,7 @@ static inline bool spimem_flash_ll_host_idle(const spi_mem_dev_t *dev)
*/
static inline void spimem_flash_ll_read_phase(spi_mem_dev_t *dev)
{
typeof (dev->user) user = {
typeof(dev->user) user = {
.usr_mosi = 0,
.usr_miso = 1,
.usr_addr = 1,
@@ -384,7 +384,7 @@ static inline void spimem_flash_ll_set_cs_pin(spi_mem_dev_t *dev, int pin)
*/
static inline void spimem_flash_ll_set_read_mode(spi_mem_dev_t *dev, esp_flash_io_mode_t read_mode)
{
typeof (dev->ctrl) ctrl;
typeof(dev->ctrl) ctrl;
ctrl.val = dev->ctrl.val;
ctrl.val &= ~(SPI_MEM_FREAD_QIO_M | SPI_MEM_FREAD_QUAD_M | SPI_MEM_FREAD_DIO_M | SPI_MEM_FREAD_DUAL_M);
ctrl.val |= SPI_MEM_FASTRD_MODE_M;
@@ -524,7 +524,9 @@ static inline void spimem_flash_ll_set_usr_address(spi_mem_dev_t *dev, uint32_t
static inline void spimem_flash_ll_set_dummy(spi_mem_dev_t *dev, uint32_t dummy_n)
{
dev->user.usr_dummy = dummy_n ? 1 : 0;
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
if (dummy_n > 0) {
HAL_FORCE_MODIFY_U32_REG_FIELD(dev->user1, usr_dummy_cyclelen, dummy_n - 1);
}
}
/**
@@ -544,7 +546,7 @@ static inline void spimem_flash_ll_set_dummy_out(spi_mem_dev_t *dev, uint32_t ou
static inline void spimem_flash_ll_set_hold(spi_mem_dev_t *dev, uint32_t hold_n)
{
dev->ctrl2.cs_hold_time = hold_n - 1;
dev->user.cs_hold = (hold_n > 0? 1: 0);
dev->user.cs_hold = (hold_n > 0 ? 1 : 0);
}
static inline void spimem_flash_ll_set_cs_setup(spi_mem_dev_t *dev, uint32_t cs_setup_time)
@@ -567,17 +569,17 @@ static inline uint8_t spimem_flash_ll_get_source_freq_mhz(void)
// In the future, we can get the CPU clock source by calling interface.
uint8_t clock_val = 0;
switch (SPIMEM0.spi_core_clk_sel.spi01_clk_sel) {
case 0:
clock_val = 80;
break;
case 1:
clock_val = 120;
break;
case 2:
clock_val = 160;
break;
default:
abort();
case 0:
clock_val = 80;
break;
case 1:
clock_val = 120;
break;
case 2:
clock_val = 160;
break;
default:
abort();
}
return clock_val;
}
@@ -596,7 +598,7 @@ static inline uint32_t spimem_flash_ll_calculate_clock_reg(uint8_t clkdiv)
if (clkdiv == 1) {
div_parameter = (1 << 31);
} else {
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8 ) | (((clkdiv - 1) & 0xff) << 16));
div_parameter = ((clkdiv - 1) | (((clkdiv - 1) / 2 & 0xff) << 8) | (((clkdiv - 1) & 0xff) << 16));
}
return div_parameter;
}