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Merge branch 'bugfix/fix_rc_fast_calibration_v5.1' into 'release/v5.1'

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rtc_clk: fix esp32c6/esp32h2 eco chip `RC_FAST` bad calibration value (backport v5.1)

See merge request espressif/esp-idf!23940
This commit is contained in:
Jiang Jiang Jian
2023-05-31 17:40:28 +08:00
parent 0d13f6f09d 8c714acfb5
commit 5cd24826bb
4 changed files with 58 additions and 60 deletions
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20
components/soc/esp32h2/include/soc/rtc.h
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@@ -393,26 +393,6 @@ void rtc_clk_cpu_freq_set_xtal(void);
*/
uint32_t rtc_clk_apb_freq_get(void);
/**
* @brief Clock calibration function used by rtc_clk_cal
*
* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
* This feature counts the number of XTAL clock cycles within a given number of
* RTC_SLOW_CLK cycles.
*
* Slow clock calibration feature has two modes of operation: one-off and cycling.
* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
* enabled using TIMG_RTC_CALI_START bit.
*
* @param cal_clk which clock to calibrate
* @param slowclk_cycles number of slow clock cycles to count
* @return number of XTAL clock cycles within the given number of slow clock cycles
*/
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
/**
* @brief Measure RTC slow clock's period, based on main XTAL frequency
*