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refactor(riscv): refactor crosscore interrupt

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This commit is contained in:
Omar Chebib
2023-12-11 19:37:30 +08:00
parent 298931596a
commit 5cdf145f55
13 changed files with 415 additions and 68 deletions
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45
components/hal/esp32/include/hal/crosscore_int_ll.h Normal file
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/*
* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "esp_attr.h"
#include "soc/dport_reg.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @brief Clear the crosscore interrupt that just occurred on the current core
*/
FORCE_INLINE_ATTR void crosscore_int_ll_clear_interrupt(int core_id)
{
if (core_id == 0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, 0);
} else {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, 0);
}
}
/**
* @brief Trigger a crosscore interrupt on the given core
*
* @param core_id Core to trigger an interrupt on. Ignored on single core targets.
*/
FORCE_INLINE_ATTR void crosscore_int_ll_trigger_interrupt(int core_id)
{
if (core_id == 0) {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_0_REG, DPORT_CPU_INTR_FROM_CPU_0);
} else {
DPORT_WRITE_PERI_REG(DPORT_CPU_INTR_FROM_CPU_1_REG, DPORT_CPU_INTR_FROM_CPU_1);
}
}
#ifdef __cplusplus
}
#endif