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feat(esp_hw_support): add esp32p4 pau initial support

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This commit is contained in:
wuzhenghui
2024-02-06 10:49:33 +08:00
parent acd263d006
commit 5d24a818eb
16 changed files with 306 additions and 20 deletions
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8
components/hal/esp32p4/include/hal/clk_gate_ll.h
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@@ -47,6 +47,8 @@ static inline uint32_t periph_ll_get_clk_en_mask(periph_module_t periph)
return HP_SYS_CLKRST_REG_CRYPTO_ECDSA_CLK_EN;
case PERIPH_ISP_MODULE:
return HP_SYS_CLKRST_REG_ISP_CLK_EN;
case PERIPH_REGDMA_MODULE:
return HP_SYS_CLKRST_REG_REGDMA_SYS_CLK_EN;
default:
return 0;
}
@@ -103,6 +105,8 @@ static inline uint32_t periph_ll_get_rst_en_mask(periph_module_t periph, bool en
return HP_SYS_CLKRST_REG_RST_EN_ECDSA;
case PERIPH_EMAC_MODULE:
return LP_CLKRST_RST_EN_EMAC;
case PERIPH_REGDMA_MODULE:
return HP_SYS_CLKRST_REG_RST_EN_REGDMA;
default:
return 0;
}
@@ -128,6 +132,8 @@ static inline uint32_t periph_ll_get_clk_en_reg(periph_module_t periph)
return HP_SYS_CLKRST_PERI_CLK_CTRL25_REG;
case PERIPH_EMAC_MODULE:
return LP_CLKRST_HP_CLK_CTRL_REG;
case PERIPH_REGDMA_MODULE:
return HP_SYS_CLKRST_SOC_CLK_CTRL0_REG;
default:
abort();
return 0;
@@ -154,6 +160,8 @@ static inline uint32_t periph_ll_get_rst_en_reg(periph_module_t periph)
return HP_SYS_CLKRST_HP_RST_EN2_REG;
case PERIPH_EMAC_MODULE:
return LP_CLKRST_HP_SDMMC_EMAC_RST_CTRL_REG;
case PERIPH_REGDMA_MODULE:
return HP_SYS_CLKRST_HP_RST_EN0_REG;
default:
abort();
return 0;

25
components/hal/esp32p4/include/hal/lp_sys_ll.h
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@@ -34,6 +34,31 @@ static inline void lp_sys_ll_inform_wakeup_type(bool dslp)
}
}
static inline void lp_sys_ll_set_pau_aon_bypass(bool bypass)
{
LP_SYS.backup_dma_cfg1.aon_bypass = bypass ? 1 : 0;
}
static inline void lp_sys_ll_set_pau_link_tout_thres(uint32_t tout)
{
LP_SYS.backup_dma_cfg0.link_tout_thres_aon = tout;
}
static inline void lp_sys_ll_set_pau_link_backup_tout_thres(uint32_t tout)
{
LP_SYS.backup_dma_cfg0.link_backup_tout_thres_aon = tout;
}
static inline void lp_sys_ll_set_pau_reg_read_interval(uint32_t val)
{
LP_SYS.backup_dma_cfg0.read_interval_aon = val;
}
static inline void lp_sys_ll_set_pau_link_addr(uint32_t addr)
{
LP_SYS.backup_dma_cfg2.link_addr_aon = addr;
}
#ifdef __cplusplus
}
#endif

150
components/hal/esp32p4/include/hal/pau_ll.h Normal file
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@@ -0,0 +1,150 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The LL layer for ESP32-C6 PAU(Power Assist Unit) register operations
#pragma once
#include <stdlib.h>
#include <stdbool.h>
#include "soc/soc.h"
#include "soc/pau_reg.h"
#include "soc/pau_struct.h"
#include "hal/pau_types.h"
#include "hal/assert.h"
#ifdef __cplusplus
extern "C" {
#endif
static inline uint32_t pau_ll_get_regdma_backup_flow_error(pau_dev_t *dev)
{
return dev->regdma_conf.flow_err;
}
static inline void pau_ll_select_regdma_entry_link(pau_dev_t *dev, int link)
{
dev->regdma_conf.link_sel = link;
}
static inline void pau_ll_set_regdma_entry_link_backup_direction(pau_dev_t *dev, bool to_mem)
{
dev->regdma_conf.to_mem = to_mem ? 1 : 0;
}
static inline void pau_ll_set_regdma_entry_link_backup_start_enable(pau_dev_t *dev)
{
dev->regdma_conf.start = 1;
}
static inline void pau_ll_set_regdma_entry_link_backup_start_disable(pau_dev_t *dev)
{
dev->regdma_conf.start = 0;
}
static inline void pau_ll_set_regdma_select_wifimac_link(pau_dev_t *dev)
{
dev->regdma_conf.sel_mac = 1;
}
static inline void pau_ll_set_regdma_deselect_wifimac_link(pau_dev_t *dev)
{
dev->regdma_conf.sel_mac = 0;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_direction(pau_dev_t *dev, bool to_mem)
{
dev->regdma_conf.to_mem_mac = to_mem ? 1 : 0;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_start_enable(pau_dev_t *dev)
{
dev->regdma_conf.start_mac = 1;
}
static inline void pau_ll_set_regdma_wifimac_link_backup_start_disable(pau_dev_t *dev)
{
dev->regdma_conf.start_mac = 0;
}
static inline void pau_ll_set_regdma_link0_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_0_addr.val = (uint32_t)link_addr;
}
static inline void pau_ll_set_regdma_link1_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_1_addr.val = (uint32_t)link_addr;
}
static inline void pau_ll_set_regdma_link2_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_2_addr.val = (uint32_t)link_addr;
}
static inline void pau_ll_set_regdma_link3_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_3_addr.val = (uint32_t)link_addr;
}
static inline void pau_ll_set_regdma_wifimac_link_addr(pau_dev_t *dev, void *link_addr)
{
dev->regdma_link_mac_addr.val = (uint32_t)link_addr;
}
static inline uint32_t pau_ll_get_regdma_current_link_addr(pau_dev_t *dev)
{
return dev->regdma_current_link_addr.val;
}
static inline uint32_t pau_ll_get_regdma_backup_addr(pau_dev_t *dev)
{
return dev->regdma_backup_addr.val;
}
static inline uint32_t pau_ll_get_regdma_memory_addr(pau_dev_t *dev)
{
return dev->regdma_mem_addr.val;
}
static inline uint32_t pau_ll_get_regdma_intr_raw_signal(pau_dev_t *dev)
{
return dev->int_raw.val;
}
static inline uint32_t pau_ll_get_regdma_intr_status(pau_dev_t *dev)
{
return dev->int_st.val;
}
static inline void pau_ll_set_regdma_backup_done_intr_enable(pau_dev_t *dev)
{
dev->int_ena.done_int_ena = 1;
}
static inline void pau_ll_set_regdma_backup_done_intr_disable(pau_dev_t *dev)
{
dev->int_ena.done_int_ena = 0;
}
static inline void pau_ll_set_regdma_backup_error_intr_enable(pau_dev_t *dev, bool enable)
{
dev->int_ena.error_int_ena = enable;
}
static inline void pau_ll_clear_regdma_backup_done_intr_state(pau_dev_t *dev)
{
dev->int_clr.done_int_clr = 1;
}
static inline void pau_ll_clear_regdma_backup_error_intr_state(pau_dev_t *dev)
{
dev->int_clr.error_int_clr = 1;
}
#ifdef __cplusplus
}
#endif

72
components/hal/esp32p4/pau_hal.c Normal file
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@@ -0,0 +1,72 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The HAL layer for PAU (ESP32-C6 specific part)
#include "soc/soc.h"
#include "soc/soc_caps.h"
#include "esp_attr.h"
#include "hal/pau_hal.h"
#include "hal/pau_types.h"
#if SOC_PAU_IN_TOP_DOMAIN
#include "hal/lp_sys_ll.h"
#endif
void pau_hal_set_regdma_entry_link_addr(pau_hal_context_t *hal, pau_regdma_link_addr_t *link_addr)
{
pau_ll_set_regdma_link0_addr(hal->dev, (*link_addr)[0]);
pau_ll_set_regdma_link1_addr(hal->dev, (*link_addr)[1]);
pau_ll_set_regdma_link2_addr(hal->dev, (*link_addr)[2]);
/* The link 3 of REGDMA is reserved, PMU state switching will not use
* REGDMA link 3 */
}
void IRAM_ATTR pau_hal_start_regdma_modem_link(pau_hal_context_t *hal, bool backup_or_restore)
{
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
pau_ll_set_regdma_select_wifimac_link(hal->dev);
pau_ll_set_regdma_wifimac_link_backup_direction(hal->dev, backup_or_restore);
pau_ll_set_regdma_wifimac_link_backup_start_enable(hal->dev);
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
}
void IRAM_ATTR pau_hal_stop_regdma_modem_link(pau_hal_context_t *hal)
{
pau_ll_set_regdma_wifimac_link_backup_start_disable(hal->dev);
pau_ll_set_regdma_deselect_wifimac_link(hal->dev);
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
}
void IRAM_ATTR pau_hal_start_regdma_extra_link(pau_hal_context_t *hal, bool backup_or_restore)
{
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
/* The link 3 of REGDMA is reserved, we use it as an extra linked list to
* provide backup and restore services for BLE, IEEE802.15.4 and possibly
* other modules */
pau_ll_select_regdma_entry_link(hal->dev, 3);
pau_ll_set_regdma_entry_link_backup_direction(hal->dev, backup_or_restore);
pau_ll_set_regdma_entry_link_backup_start_enable(hal->dev);
while (!(pau_ll_get_regdma_intr_raw_signal(hal->dev) & PAU_DONE_INT_RAW));
}
void IRAM_ATTR pau_hal_stop_regdma_extra_link(pau_hal_context_t *hal)
{
pau_ll_set_regdma_entry_link_backup_start_disable(hal->dev);
pau_ll_select_regdma_entry_link(hal->dev, 3); /* restore link select to default */
pau_ll_clear_regdma_backup_done_intr_state(hal->dev);
}
#if SOC_PAU_IN_TOP_DOMAIN
void IRAM_ATTR pau_hal_lp_sys_initialize(void)
{
lp_sys_ll_set_pau_aon_bypass(true);
lp_sys_ll_set_pau_link_backup_tout_thres(300);
lp_sys_ll_set_pau_link_tout_thres(200);
lp_sys_ll_set_pau_reg_read_interval(50);
}
#endif