alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-10 04:43:33 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feat/xip_psram_c5' into 'master'

Browse Source 
psram: xip_psram support on c5/c61, also fixed cache writeback/invalidate not work issue on c61

Closes IDF-8688, IDF-9292, and IDF-11008

See merge request espressif/esp-idf!33265
This commit is contained in:
Armando (Dou Yiwen)
2024-09-06 10:39:57 +08:00
parent c2b5339275 5316a36175
commit 5dff189341
23 changed files with 236 additions and 15 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
components/soc/esp32c5/include/soc/ext_mem_defs.h
View File

@@ -58,7 +58,7 @@ extern "C" {
* valid bit + value bits
* valid bit is BIT(9), so value bits are 0x1ff
*/
#define SOC_MMU_VALID_VAL_MASK (SOC_MMU_ACCESS_SPIRAM-1)
#define SOC_MMU_VALID_VAL_MASK (SOC_MMU_ACCESS_SPIRAM - 1)
/**
* Max MMU available paddr page num.
* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
@@ -72,7 +72,7 @@ extern "C" {
* This is the mask used for mapping. e.g.:
* 0x4200_0000 & SOC_MMU_VADDR_MASK
*/
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
#define SOC_MMU_VADDR_MASK ((SOC_MMU_PAGE_SIZE) * SOC_MMU_ENTRY_NUM - 1)
#define SOC_MMU_DBUS_VADDR_BASE 0x42000000
#define SOC_MMU_IBUS_VADDR_BASE 0x42000000