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wdt: add support for WDTs on C6
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@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -17,6 +17,7 @@ extern "C" {
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#include <stdbool.h>
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#include "soc/timer_periph.h"
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#include "soc/timer_group_struct.h"
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#include "soc/pcr_struct.h"
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#include "hal/wdt_types.h"
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#include "hal/assert.h"
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#include "esp_attr.h"
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@@ -249,6 +250,55 @@ FORCE_INLINE_ATTR void mwdt_ll_set_intr_enable(timg_dev_t *hw, bool enable)
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hw->int_ena_timers.wdt_int_ena = (enable) ? 1 : 0;
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}
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/**
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* @brief Set the clock source for the MWDT.
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*
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* @param hw Beginning address of the peripheral registers.
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* @param clk_src Clock source
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*/
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FORCE_INLINE_ATTR void mwdt_ll_set_clock_source(timg_dev_t *hw, mwdt_clock_source_t clk_src)
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{
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uint8_t clk_id = 0;
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switch (clk_src) {
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case MWDT_CLK_SRC_XTAL:
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clk_id = 0;
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break;
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case MWDT_CLK_SRC_PLL_F80M:
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clk_id = 1;
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break;
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case MWDT_CLK_SRC_RC_FAST:
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clk_id = 2;
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break;
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default:
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HAL_ASSERT(false);
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break;
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}
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if (hw == &TIMERG0) {
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PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_sel = clk_id;
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} else {
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PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_sel = clk_id;
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}
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}
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/**
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* @brief Enable MWDT module clock
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*
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* @param hw Beginning address of the peripheral registers.
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* @param en true to enable, false to disable
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*/
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__attribute__((always_inline))
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static inline void mwdt_ll_enable_clock(timg_dev_t *hw, bool en)
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{
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if (hw == &TIMERG0) {
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PCR.timergroup0_wdt_clk_conf.tg0_wdt_clk_en = en;
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} else {
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PCR.timergroup1_wdt_clk_conf.tg1_wdt_clk_en = en;
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}
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}
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#ifdef __cplusplus
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}
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#endif
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