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feat(axi_icm): AXI interconnect QoS configuration functions
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morris
180
components/hal/esp32p4/include/hal/axi_icm_ll.h
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components/hal/esp32p4/include/hal/axi_icm_ll.h
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/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stddef.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include "hal/assert.h"
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#include "soc/icm_sys_qos_struct.h"
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#include "soc/icm_sys_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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typedef enum {
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AXI_ICM_MASTER_CPU = 0, // An aggregate master port for other users, like HP CPU, LP CPU, USB, EMAC, SDMMC, AHB-GDMA, etc
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AXI_ICM_MASTER_CACHE = 1, // Cache master port
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AXI_ICM_MASTER_DW_GDMA_M0 = 5, // DW-GDMA master port 0
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AXI_ICM_MASTER_DW_GDMA_M1 = 6, // DW-GDMA master port 1
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AXI_ICM_MASTER_GDMA = 8, // AXI-GDMA
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AXI_ICM_MASTER_DMA2D = 10, // DMA2D
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AXI_ICM_MASTER_H264_M0 = 11, // H264 master port 0
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AXI_ICM_MASTER_H264_M1 = 12, // H264 master port 1
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} axi_icm_ll_master_id_t;
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/**
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* @brief Set QoS burstiness for a master port, also enable the regulator
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*
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* @param mid Master port ID
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* @param burstiness Burstiness value. It represents the depth of the token bucket.
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*/
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static inline void axi_icm_ll_set_qos_burstiness(axi_icm_ll_master_id_t mid, uint32_t burstiness)
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{
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HAL_ASSERT(burstiness >= 1 && burstiness <= 256);
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// wait for the previous command to finish
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while (AXI_ICM_QOS.cmd.reg_axi_cmd_en);
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// write data register
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// data[23:16] - burstiness, data[0] - enable regulator
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AXI_ICM_QOS.data.val = (burstiness - 1) << 16 | 0x1;
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// command write operation
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AXI_ICM_QOS.cmd.reg_axi_rd_wr_cmd = 1;
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// write addr channel
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AXI_ICM_QOS.cmd.reg_rd_wr_chan = 1;
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// select master port
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AXI_ICM_QOS.cmd.reg_axi_master_port = mid;
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// set command type: burstiness regulator
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AXI_ICM_QOS.cmd.reg_axi_cmd = 0;
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// command enable bit
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AXI_ICM_QOS.cmd.reg_axi_cmd_en = 1;
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// wait for the data to be synced to internal register
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while (AXI_ICM_QOS.cmd.reg_axi_cmd_en);
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}
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/**
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* @brief Set QoS peak and transaction rate for a master port
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*
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* @note Relationship between "level" and fractional rate:
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* level = 0: 1/2
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* level = 1: 1/4
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* ...
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* level = 11: 1/4096
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*
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* @note if the transaction rate is set to 1/N, every N cycles, the master port can accept one transfer request (offer a token).
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*
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* @param mid Master port ID
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* @param peak_level Peak level, lower value means higher rate
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* @param transaction_level Transaction level, lower value means higher rate
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*/
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static inline void axi_icm_ll_set_qos_peak_transaction_rate(axi_icm_ll_master_id_t mid, uint32_t peak_level, uint32_t transaction_level)
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{
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HAL_ASSERT(peak_level < transaction_level && transaction_level <= 11);
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while (AXI_ICM_QOS.cmd.reg_axi_cmd_en);
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// program data register
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// data[31:20] - peak_rate, data[15:4] - transaction_rate
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AXI_ICM_QOS.data.val = (0x80000000 >> peak_level) + (0x8000 >> transaction_level);
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// command write operation
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AXI_ICM_QOS.cmd.reg_axi_rd_wr_cmd = 1;
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// write addr channel
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AXI_ICM_QOS.cmd.reg_rd_wr_chan = 1;
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// select master port
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AXI_ICM_QOS.cmd.reg_axi_master_port = mid;
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// set command type: peak rate xct rate
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AXI_ICM_QOS.cmd.reg_axi_cmd = 1;
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// command enable bit
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AXI_ICM_QOS.cmd.reg_axi_cmd_en = 1;
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// wait for the data to be synced to internal register
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while (AXI_ICM_QOS.cmd.reg_axi_cmd_en);
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}
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/**
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* @brief Set QoS priority for DMA2D master port
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*
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* @param write_prio Write priority
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* @param read_prio Read priority
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*/
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static inline void axi_icm_ll_set_dma2d_qos_arbiter_prio(uint32_t write_prio, uint32_t read_prio)
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{
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AXI_ICM.mst_awqos_reg0.reg_dma2d_awqos = write_prio;
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AXI_ICM.mst_arqos_reg0.reg_dma2d_arqos = read_prio;
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}
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/**
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* @brief Set QoS priority for AXI-GDMA master port
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*
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* @param write_prio Write priority
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* @param read_prio Read priority
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*/
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static inline void axi_icm_ll_set_gdma_qos_arbiter_prio(uint32_t write_prio, uint32_t read_prio)
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{
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AXI_ICM.mst_awqos_reg0.reg_pdma_int_awqos = write_prio;
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AXI_ICM.mst_arqos_reg0.reg_axi_pdma_int_arqos = read_prio;
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}
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/**
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* @brief Set QoS priority for DW_GDMA master port
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*
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* @param master_port DW_GDMA master port ID
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* @param write_prio Write priority
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* @param read_prio Read priority
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*/
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static inline void axi_icm_ll_set_dw_gdma_qos_arbiter_prio(uint32_t master_port, uint32_t write_prio, uint32_t read_prio)
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{
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if (master_port == 0) {
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AXI_ICM.mst_awqos_reg0.reg_gdma_mst1_awqos = write_prio;
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AXI_ICM.mst_arqos_reg0.reg_gdma_mst1_arqos = read_prio;
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} else {
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AXI_ICM.mst_awqos_reg0.reg_gdma_mst2_awqos = write_prio;
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AXI_ICM.mst_arqos_reg0.reg_gdma_mst2_arqos = read_prio;
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}
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}
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/**
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* @brief Set QoS priority for H264 master port
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*
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* @param master_port H264 master port ID
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* @param write_prio Write priority
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* @param read_prio Read priority
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*/
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static inline void axi_icm_ll_set_h264_dma_qos_arbiter_prio(uint32_t master_port, uint32_t write_prio, uint32_t read_prio)
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{
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if (master_port == 0) {
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AXI_ICM.mst_awqos_reg0.reg_h264_dma2d_m1_awqos = write_prio;
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AXI_ICM.mst_arqos_reg0.reg_h264_dma2d_m1_arqos = read_prio;
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} else {
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AXI_ICM.mst_awqos_reg0.reg_h264_dma2d_m2_awqos = write_prio;
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AXI_ICM.mst_arqos_reg0.reg_h264_dma2d_m2_arqos = read_prio;
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}
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}
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/**
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* @brief Set QoS priority for Cache master port
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*
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* @param write_prio Write priority
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* @param read_prio Read priority
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*/
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static inline void axi_icm_ll_set_cache_qos_arbiter_prio(uint32_t write_prio, uint32_t read_prio)
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{
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AXI_ICM.mst_awqos_reg0.reg_cache_awqos = write_prio;
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AXI_ICM.mst_arqos_reg0.reg_cache_arqos = read_prio;
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}
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/**
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* @brief Set QoS priority for CPU master port
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*
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* @param write_prio Write priority
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* @param read_prio Read priority
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*/
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static inline void axi_icm_ll_set_cpu_qos_arbiter_prio(uint32_t write_prio, uint32_t read_prio)
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{
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AXI_ICM.mst_awqos_reg0.reg_cpu_awqos = write_prio;
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AXI_ICM.mst_arqos_reg0.reg_cpu_arqos = read_prio;
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}
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#ifdef __cplusplus
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}
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#endif
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