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clk_tree: prework of introducing clk subsystem control
1. Clean up clk usage in IDF, replace rtc_clk_xtal/apb_freq_get with upper level API esp_clk_xtal/apb_freq 2. Fix small errors and wrong comments related to clock 3. Add clk_tree_defs.h to provide an unified clock id for each chip Modify the NGed drivers to adopt new clock ids
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124
components/soc/esp32c2/include/soc/clk_tree_defs.h
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124
components/soc/esp32c2/include/soc/clk_tree_defs.h
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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************************ ESP32C2 Root Clock Source ***************************
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* 1) Internal 20MHz RC Oscillator: RC_FAST (usually referred as FOSC or CK8M/CLK8M in TRM and reg. description)
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*
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* This RC oscillator generates a ~17.5MHz clock signal output as the RC_FAST_CLK.
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* The ~17.5MHz signal output is also passed into a configurable divider, which by default divides the input clock
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* frequency by 256, to generate a RC_FAST_D256_CLK (usually referred as 8md256 or simply d256 in reg. description).
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*
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* The exact frequency of RC_FAST_CLK can be computed in runtime through calibration on the RC_FAST_D256_CLK.
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*
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* 2) External 40MHz Crystal Clock: XTAL
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*
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* 3) Internal 1500kHz RC Oscillator: RC_SLOW (usually referrred as RTC in TRM or reg. description)
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*
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* This RC oscillator generates a ~150kHz clock signal output as the RC_SLOW_CLK. The exact frequency of this clock
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* can be computed in runtime through calibration.
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*
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* 4) External Slow Clock (optional): XTAL32K
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*
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* A clock signal generated by an external circuit can be connected to the 32K_XN pin to be the clock source for the
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* RTC_SLOW_CLK. In such case, a 1nF capacitor should be placed between the 32K_XN pin and ground, so the 32K_XP pin
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* cannot be used as a GPIO pin.
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*
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* XTAL32K_CLK can also be calibrated to get its exact frequency.
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*/
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/* With the default value of CK8M_DFREQ = 100, RC_FAST clock frequency is 17.5 MHz +/- 7% */
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#define SOC_CLK_RC_FAST_FREQ_APPROX 17500000
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#define SOC_CLK_RC_SLOW_FREQ_APPROX 150000
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#define SOC_CLK_RC_FAST_D256_FREQ_APPROX (SOC_CLK_RC_FAST_FREQ_APPROX / 256)
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#define SOC_CLK_XTAL32K_FREQ_APPROX 32768
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/**
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* @brief Root clock
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* Naming convention: SOC_ROOT_CLK_{loc}_{type}_<attr>
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* {loc}: EXT, INT
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* {type}: XTAL, RC
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* <attr> - optional: <frequency>, FAST, SLOW
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*/
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typedef enum {
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SOC_ROOT_CLK_INT_RC_FAST, /*!< Internal 8MHz RC oscillator */
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SOC_ROOT_CLK_INT_RC_SLOW, /*!< Internal 150kHz RC oscillator */
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SOC_ROOT_CLK_EXT_XTAL, /*!< External 40MHz crystal */
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SOC_ROOT_CLK_EXT_XTAL32K, /*!< External ~32kHz clock signal */
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} soc_root_clk_t;
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/**
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* @brief CPU_CLK mux inputs, which are the supported clock sources for the CPU_CLK
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*/
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typedef enum {
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SOC_CPU_CLK_SRC_XTAL, /*!< Select XTAL_CLK as CPU_CLK source */
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SOC_CPU_CLK_SRC_PLL, /*!< Select PLL_CLK as CPU_CLK source (PLL_CLK is the output of 40MHz crystal oscillator frequency multiplier, 480MHz) */
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SOC_CPU_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as CPU_CLK source */
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} soc_cpu_clk_src_t;
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/**
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* @brief RTC_SLOW_CLK mux inputs, which are the supported clock sources for the RTC_SLOW_CLK
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*/
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typedef enum {
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SOC_RTC_SLOW_CLK_SRC_RC_SLOW, /*!< Select RC_SLOW_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_XTAL32K, /*!< Select XTAL32K_CLK as RTC_SLOW_CLK source */
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SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256, /*!< Select RC_FAST_D256_CLK (referred as FOSC_DIV or 8m_d256/8md256 in TRM and reg. description) as RTC_SLOW_CLK source */
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} soc_rtc_slow_clk_src_t;
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/**
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* @brief RTC_FAST_CLK mux inputs, which are the supported clock sources for the RTC_FAST_CLK
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*/
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typedef enum {
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SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Select XTAL_D2_CLK (may referred as XTAL_CLK_DIV_2) as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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SOC_RTC_FAST_CLK_SRC_RC_FAST, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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} soc_rtc_fast_clk_src_t;
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/**
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* @brief Supported clock sources for modules (CPU, peripherials, RTC, etc.)
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* Naming convention: SOC_MOD_CLK_{<upstream>clock_name}_<attr>
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* {<upstream>clock_name}: (BB)PLL etc.
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* <attr> - optional: FAST, SLOW, D<divider>, F<freq>
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*/
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typedef enum {
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// For CPU domain
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SOC_MOD_CLK_CPU = 1, /*< CPU_CLK can be sourced from XTAL, PLL, or RC_FAST by configuring soc_cpu_clk_src_t */
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// For RTC domain
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SOC_MOD_CLK_RTC_FAST = 2, /*< RTC_FAST_CLK can be sourced from XTAL_D2 or RC_FAST by configuring soc_rtc_fast_clk_src_t */
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SOC_MOD_CLK_RTC_SLOW = 3, /*< RTC_SLOW_CLK can be sourced from RC_SLOW, XTAL32K, or RC_FAST_D256 by configuring soc_rtc_slow_clk_src_t */
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// For digital domain: peripherals, WIFI, BLE
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SOC_MOD_CLK_PLL_F40M = 4, /*< PLL_F40M_CLK is derived from PLL, and has a fixed frequency of 40MHz */
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SOC_MOD_CLK_PLL_F60M = 5, /*< PLL_F60M_CLK is derived from PLL, and has a fixed frequency of 60MHz */
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SOC_MOD_CLK_PLL_F80M = 6, /*< PLL_F80M_CLK is derived from PLL, and has a fixed frequency of 80MHz */
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SOC_MOD_CLK_XTAL32K = 7, /*< XTAL32K_CLK comes from the external 32kHz clock signal, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST = 8, /*< RC_FAST_CLK comes from the internal 20MHz rc oscillator, passing a clock gating to the peripherals */
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SOC_MOD_CLK_RC_FAST_D256 = 9, /*< RC_FAST_D256_CLK comes from the internal 20MHz rc oscillator, divided by 256, and passing a clock gating to the peripherals */
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SOC_MOD_CLK_XTAL = 10, /*< XTAL_CLK comes from the external 40MHz crystal */
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} soc_module_clk_t;
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// List clock sources available to each peripherial
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// soc_module_clk_src_t enum starts from 1 to save enum = 0 for AUTO selection
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typedef enum {
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GPTIMER_CLK_SRC_APB = SOC_MOD_CLK_PLL_F40M, /*!< Select APB as the source clock */
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GPTIMER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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} soc_periph_gptimer_clk_src_t;
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typedef enum {
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TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = 0, /*!< Use default clock selection */
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TEMPERATURE_SENSOR_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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TEMPERATURE_SENSOR_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
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} soc_periph_temperature_sensor_clk_src_t;
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#ifdef __cplusplus
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}
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#endif
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