clk_tree: prework of introducing clk subsystem control

1. Clean up clk usage in IDF, replace rtc_clk_xtal/apb_freq_get with
   upper level API esp_clk_xtal/apb_freq
2. Fix small errors and wrong comments related to clock
3. Add clk_tree_defs.h to provide an unified clock id for each chip
   Modify the NGed drivers to adopt new clock ids

components/soc/esp32c3/include/soc/rtc_cntl_struct.h

@@ -1,16 +1,8 @@
-// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-//
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
+/*
+ * SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
 #ifndef _SOC_RTC_CNTL_STRUCT_H_
 #define _SOC_RTC_CNTL_STRUCT_H_
 #ifdef __cplusplus
@@ -335,7 +327,7 @@ typedef volatile struct rtc_cntl_dev_s {
             uint32_t ck8m_force_pu:              1;        /*CK8M force power up*/
             uint32_t xtal_global_force_gating:   1;
             uint32_t xtal_global_force_nogating: 1;
-            uint32_t fast_clk_rtc_sel:           1;        /*fast_clk_rtc sel. 0: XTAL div 4*/
+            uint32_t fast_clk_rtc_sel:           1;        /*fast_clk_rtc sel. 0: XTAL div 2*/
             uint32_t ana_clk_rtc_sel:            2;
         };
         uint32_t val;