mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-12 13:27:36 +00:00
make bootloader_support support esp32s2beta
This commit is contained in:
suda-morris
@@ -19,6 +19,7 @@
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#include "esp_attr.h"
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#include "esp_log.h"
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#if CONFIG_IDF_TARGET_ESP32
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#include "esp32/rom/cache.h"
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#include "esp32/rom/efuse.h"
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#include "esp32/rom/ets_sys.h"
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@@ -28,6 +29,19 @@
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#include "esp32/rom/uart.h"
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#include "esp32/rom/gpio.h"
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#include "esp32/rom/secure_boot.h"
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#include "esp32s2beta/rom/cache.h"
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#include "esp32s2beta/rom/efuse.h"
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#include "esp32s2beta/rom/ets_sys.h"
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#include "esp32s2beta/rom/spi_flash.h"
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#include "esp32s2beta/rom/crc.h"
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#include "esp32s2beta/rom/rtc.h"
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#include "esp32s2beta/rom/uart.h"
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#include "esp32s2beta/rom/gpio.h"
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#include "esp32s2beta/rom/secure_boot.h"
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#else
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#error "Unsupported IDF_TARGET"
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#endif
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#include "soc/soc.h"
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#include "soc/cpu.h"
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@@ -39,6 +53,11 @@
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#include "soc/timer_periph.h"
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#include "soc/rtc_wdt.h"
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#include "soc/spi_periph.h"
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#if CONFIG_IDF_TARGET_ESP32S2BETA
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#include "soc/spi_mem_reg.h"
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#include "soc/extmem_reg.h"
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#include "soc/assist_debug_reg.h"
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#endif
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#include "sdkconfig.h"
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#include "esp_image_format.h"
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@@ -48,6 +67,7 @@
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#include "bootloader_flash.h"
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#include "bootloader_random.h"
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#include "bootloader_config.h"
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#include "bootloader_common.h"
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#include "bootloader_clock.h"
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#include "bootloader_common.h"
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@@ -58,12 +78,13 @@ extern int _bss_end;
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extern int _data_start;
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extern int _data_end;
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static const char* TAG = "boot";
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static const char *TAG = "boot";
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static esp_err_t bootloader_main();
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static void print_flash_info(const esp_image_header_t* pfhdr);
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static void update_flash_config(const esp_image_header_t* pfhdr);
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static void flash_gpio_configure(const esp_image_header_t* pfhdr);
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static void print_flash_info(const esp_image_header_t *pfhdr);
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static void update_flash_config(const esp_image_header_t *pfhdr);
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static void vddsdio_configure();
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static void flash_gpio_configure(const esp_image_header_t *pfhdr);
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static void uart_console_configure(void);
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static void wdt_reset_check(void);
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@@ -79,8 +100,10 @@ esp_err_t bootloader_init()
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int *sp = get_sp();
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assert(&_bss_start <= &_bss_end);
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assert(&_data_start <= &_data_end);
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#if CONFIG_IDF_TARGET_ESP32
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assert(sp < &_bss_start);
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assert(sp < &_data_start);
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#endif
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}
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#endif
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@@ -89,14 +112,27 @@ esp_err_t bootloader_init()
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/* completely reset MMU for both CPUs
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(in case serial bootloader was running) */
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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#if !CONFIG_FREERTOS_UNICORE
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Cache_Read_Disable(1);
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#endif
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Cache_Flush(0);
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#if !CONFIG_FREERTOS_UNICORE
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Cache_Flush(1);
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#endif
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mmu_init(0);
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#if !CONFIG_FREERTOS_UNICORE
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DPORT_REG_SET_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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mmu_init(1);
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MMU_IA_CLR);
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#endif
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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//TODO, save the autoload value
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Cache_Suspend_ICache();
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Cache_Invalidate_ICache_All();
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Cache_MMU_Init();
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#endif
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/* (above steps probably unnecessary for most serial bootloader
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usage, all that's absolutely needed is that we unmask DROM0
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cache on the following two lines - normal ROM boot exits with
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@@ -107,10 +143,18 @@ esp_err_t bootloader_init()
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The lines which manipulate DPORT_APP_CACHE_MMU_IA_CLR bit are
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necessary to work around a hardware bug.
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*/
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#if CONFIG_IDF_TARGET_ESP32
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DPORT_REG_CLR_BIT(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DROM0);
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#if !CONFIG_FREERTOS_UNICORE
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DPORT_REG_CLR_BIT(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DROM0);
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if(bootloader_main() != ESP_OK){
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#endif
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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DPORT_REG_CLR_BIT(DPORT_PRO_ICACHE_CTRL1_REG, DPORT_PRO_ICACHE_MASK_DROM0);
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#if !CONFIG_FREERTOS_UNICORE
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DPORT_REG_CLR_BIT(DPORT_APP_ICACHE_CTRL1_REG, DPORT_APP_ICACHE_MASK_DROM0);
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#endif
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#endif
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if (bootloader_main() != ESP_OK) {
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return ESP_FAIL;
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}
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return ESP_OK;
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@@ -127,23 +171,25 @@ static esp_err_t bootloader_main()
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return ESP_FAIL;
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}
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flash_gpio_configure(&fhdr);
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#if (CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ == 240)
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//Check if ESP32 is rated for a CPU frequency of 160MHz only
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if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
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REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
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ESP_LOGE(TAG, "Chip CPU frequency rated for 160MHz. Modify CPU frequency in menuconfig");
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int rated_freq = bootloader_clock_get_rated_freq_mhz();
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if (rated_freq < CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ) {
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ESP_LOGE(TAG, "Chip CPU frequency rated for %dMHz, configured for %dMHz. Modify CPU frequency in menuconfig",
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rated_freq, CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ);
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return ESP_FAIL;
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}
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#endif
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bootloader_clock_configure();
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uart_console_configure();
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wdt_reset_check();
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ESP_LOGI(TAG, "ESP-IDF %s 2nd stage bootloader", IDF_VER);
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ESP_LOGI(TAG, "compile time " __TIME__ );
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#if !CONFIG_FREERTOS_UNICORE
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ets_set_appcpu_boot_addr(0);
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#endif
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#ifdef CONFIG_BOOTLOADER_WDT_ENABLE
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#if CONFIG_BOOTLOADER_WDT_ENABLE && CONFIG_IDF_TARGET_ESP32
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ESP_LOGD(TAG, "Enabling RTCWDT(%d ms)", CONFIG_BOOTLOADER_WDT_TIME_MS);
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rtc_wdt_protect_off();
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rtc_wdt_disable();
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@@ -153,7 +199,7 @@ static esp_err_t bootloader_main()
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rtc_wdt_set_time(RTC_WDT_STAGE0, CONFIG_BOOTLOADER_WDT_TIME_MS);
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rtc_wdt_enable();
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rtc_wdt_protect_on();
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#else
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#elif CONFIG_IDF_TARGET_ESP32
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/* disable watch dog here */
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rtc_wdt_disable();
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#endif
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@@ -162,7 +208,7 @@ static esp_err_t bootloader_main()
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#ifndef CONFIG_SPI_FLASH_ROM_DRIVER_PATCH
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const uint32_t spiconfig = ets_efuse_get_spiconfig();
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if(spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
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if (spiconfig != EFUSE_SPICONFIG_SPI_DEFAULTS && spiconfig != EFUSE_SPICONFIG_HSPI_DEFAULTS) {
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ESP_LOGE(TAG, "SPI flash pins are overridden. \"Enable SPI flash ROM driver patched functions\" must be enabled in menuconfig");
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return ESP_FAIL;
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}
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@@ -183,38 +229,46 @@ static esp_err_t bootloader_main()
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return ESP_OK;
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}
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static void update_flash_config(const esp_image_header_t* pfhdr)
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static void update_flash_config(const esp_image_header_t *pfhdr)
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{
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uint32_t size;
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switch(pfhdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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size = 2;
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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size = 8;
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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default:
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size = 2;
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switch (pfhdr->spi_size) {
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case ESP_IMAGE_FLASH_SIZE_1MB:
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size = 1;
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break;
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case ESP_IMAGE_FLASH_SIZE_2MB:
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size = 2;
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break;
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case ESP_IMAGE_FLASH_SIZE_4MB:
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size = 4;
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break;
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case ESP_IMAGE_FLASH_SIZE_8MB:
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size = 8;
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break;
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case ESP_IMAGE_FLASH_SIZE_16MB:
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size = 16;
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break;
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default:
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size = 2;
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}
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Cache_Read_Disable( 0 );
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Read_Disable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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uint32_t autoload = Cache_Suspend_ICache();
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#endif
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// Set flash chip size
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esp_rom_spiflash_config_param(g_rom_flashchip.device_id, size * 0x100000, 0x10000, 0x1000, 0x100, 0xffff);
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// TODO: set mode
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// TODO: set frequency
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#if CONFIG_IDF_TARGET_ESP32
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Cache_Flush(0);
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Cache_Read_Enable( 0 );
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Cache_Read_Enable(0);
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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Cache_Resume_ICache(autoload);
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#endif
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}
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static void print_flash_info(const esp_image_header_t* phdr)
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static void print_flash_info(const esp_image_header_t *phdr)
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{
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#if (BOOT_LOG_LEVEL >= BOOT_LOG_LEVEL_NOTICE)
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@@ -224,7 +278,7 @@ static void print_flash_info(const esp_image_header_t* phdr)
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ESP_LOGD(TAG, "spi_speed %02x", phdr->spi_speed );
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ESP_LOGD(TAG, "spi_size %02x", phdr->spi_size );
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const char* str;
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const char *str;
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switch ( phdr->spi_speed ) {
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case ESP_IMAGE_SPI_SPEED_40M:
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str = "40MHz";
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@@ -246,6 +300,7 @@ static void print_flash_info(const esp_image_header_t* phdr)
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/* SPI mode could have been set to QIO during boot already,
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so test the SPI registers not the flash header */
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#if CONFIG_IDF_TARGET_ESP32
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uint32_t spi_ctrl = REG_READ(SPI_CTRL_REG(0));
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if (spi_ctrl & SPI_FREAD_QIO) {
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str = "QIO";
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@@ -260,6 +315,22 @@ static void print_flash_info(const esp_image_header_t* phdr)
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} else {
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str = "SLOW READ";
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}
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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uint32_t spi_ctrl = REG_READ(SPI_MEM_CTRL_REG(0));
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if (spi_ctrl & SPI_MEM_FREAD_QIO) {
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str = "QIO";
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} else if (spi_ctrl & SPI_MEM_FREAD_QUAD) {
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str = "QOUT";
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} else if (spi_ctrl & SPI_MEM_FREAD_DIO) {
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str = "DIO";
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} else if (spi_ctrl & SPI_MEM_FREAD_DUAL) {
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str = "DOUT";
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} else if (spi_ctrl & SPI_MEM_FASTRD_MODE) {
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str = "FAST READ";
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} else {
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str = "SLOW READ";
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}
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#endif
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ESP_LOGI(TAG, "SPI Mode : %s", str );
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switch ( phdr->spi_size ) {
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@@ -286,58 +357,91 @@ static void print_flash_info(const esp_image_header_t* phdr)
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#endif
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}
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static void vddsdio_configure()
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{
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#if CONFIG_BOOTLOADER_VDDSDIO_BOOST_1_9V
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rtc_vddsdio_config_t cfg = rtc_vddsdio_get_config();
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if (cfg.enable == 1 && cfg.tieh == RTC_VDDSDIO_TIEH_1_8V) { // VDDSDIO regulator is enabled @ 1.8V
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cfg.drefh = 3;
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cfg.drefm = 3;
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cfg.drefl = 3;
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cfg.force = 1;
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rtc_vddsdio_set_config(cfg);
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ets_delay_us(10); // wait for regulator to become stable
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}
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#endif // CONFIG_BOOTLOADER_VDDSDIO_BOOST
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}
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#if CONFIG_IDF_TARGET_ESP32
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#define FLASH_CLK_IO 6
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#define FLASH_CS_IO 11
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#define FLASH_SPIQ_IO 7
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#define FLASH_SPID_IO 8
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#define FLASH_SPIWP_IO 10
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#define FLASH_SPIHD_IO 9
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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#define FLASH_IO_MATRIX_DUMMY_40M 1
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#define FLASH_IO_MATRIX_DUMMY_80M 2
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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#define FLASH_IO_MATRIX_DUMMY_40M 0
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#define FLASH_IO_MATRIX_DUMMY_80M 0
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#endif
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#define FLASH_IO_DRIVE_GD_WITH_1V8PSRAM 3
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/*
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* Bootloader reads SPI configuration from bin header, so that
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* the burning configuration can be different with compiling configuration.
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*/
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static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr)
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static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t *pfhdr)
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{
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int spi_cache_dummy = 0;
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int drv = 2;
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switch (pfhdr->spi_mode) {
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case ESP_IMAGE_SPI_MODE_QIO:
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
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break;
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case ESP_IMAGE_SPI_MODE_DIO:
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //qio 3
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break;
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case ESP_IMAGE_SPI_MODE_QOUT:
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case ESP_IMAGE_SPI_MODE_DOUT:
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default:
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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break;
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case ESP_IMAGE_SPI_MODE_QIO:
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN;
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break;
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case ESP_IMAGE_SPI_MODE_DIO:
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spi_cache_dummy = SPI0_R_DIO_DUMMY_CYCLELEN; //qio 3
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break;
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case ESP_IMAGE_SPI_MODE_QOUT:
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case ESP_IMAGE_SPI_MODE_DOUT:
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default:
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spi_cache_dummy = SPI0_R_FAST_DUMMY_CYCLELEN;
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break;
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}
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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switch (pfhdr->spi_speed) {
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case ESP_IMAGE_SPI_SPEED_80M:
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
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SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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drv = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_40M:
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M,
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SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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break;
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default:
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break;
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case ESP_IMAGE_SPI_SPEED_80M:
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_80M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_80M;
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#if CONFIG_IDF_TARGET_ESP32
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SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
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SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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#elif CONFIG_IDF_TARGET_ESP32S2BETA
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SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_80M,
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SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
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#endif
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drv = 3;
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break;
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case ESP_IMAGE_SPI_SPEED_40M:
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g_rom_spiflash_dummy_len_plus[0] = FLASH_IO_MATRIX_DUMMY_40M;
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g_rom_spiflash_dummy_len_plus[1] = FLASH_IO_MATRIX_DUMMY_40M;
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#if CONFIG_IDF_TARGET_ESP32
|
||||
SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M,
|
||||
SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
SET_PERI_REG_BITS(SPI_MEM_USER1_REG(0), SPI_MEM_USR_DUMMY_CYCLELEN_V, spi_cache_dummy + FLASH_IO_MATRIX_DUMMY_40M,
|
||||
SPI_MEM_USR_DUMMY_CYCLELEN_S); //DUMMY
|
||||
#endif
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
|
||||
uint32_t pkg_ver = chip_ver & 0x7;
|
||||
|
||||
@@ -379,7 +483,7 @@ static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr)
|
||||
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, drv, FUN_DRV_S);
|
||||
|
||||
#if CONFIG_SPIRAM_TYPE_ESPPSRAM32
|
||||
#if CONFIG_SPIRAM_TYPE_ESPPSRAM32
|
||||
uint32_t flash_id = g_rom_flashchip.device_id;
|
||||
if (flash_id == FLASH_ID_GD25LQ32C) {
|
||||
// Set drive ability for 1.8v flash in 80Mhz.
|
||||
@@ -390,9 +494,12 @@ static void IRAM_ATTR flash_gpio_configure(const esp_image_header_t* pfhdr)
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3, FUN_DRV_S);
|
||||
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
bootloader_configure_spi_pins(drv);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void uart_console_configure(void)
|
||||
@@ -450,9 +557,16 @@ static void uart_console_configure(void)
|
||||
|
||||
static void wdt_reset_cpu0_info_enable(void)
|
||||
{
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
//We do not reset core1 info here because it didn't work before cpu1 was up. So we put it into call_start_cpu1.
|
||||
DPORT_REG_SET_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_PDEBUG_ENABLE | DPORT_PRO_CPU_RECORD_ENABLE);
|
||||
DPORT_REG_CLR_BIT(DPORT_PRO_CPU_RECORD_CTRL_REG, DPORT_PRO_CPU_RECORD_ENABLE);
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
DPORT_REG_SET_BIT(DPORT_PERI_CLK_EN_REG, DPORT_PERI_EN_ASSIST_DEBUG);
|
||||
DPORT_REG_CLR_BIT(DPORT_PERI_RST_EN_REG, DPORT_PERI_EN_ASSIST_DEBUG);
|
||||
REG_WRITE(ASSIST_DEBUG_PRO_PDEBUGENABLE, 1);
|
||||
REG_WRITE(ASSIST_DEBUG_PRO_RCD_RECORDING, 1);
|
||||
#endif
|
||||
}
|
||||
|
||||
static void wdt_reset_info_dump(int cpu)
|
||||
@@ -461,6 +575,7 @@ static void wdt_reset_info_dump(int cpu)
|
||||
lsstat = 0, lsaddr = 0, lsdata = 0, dstat = 0;
|
||||
const char *cpu_name = cpu ? "APP" : "PRO";
|
||||
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
if (cpu == 0) {
|
||||
stat = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_STATUS_REG);
|
||||
pid = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PID_REG);
|
||||
@@ -473,6 +588,7 @@ static void wdt_reset_info_dump(int cpu)
|
||||
lsdata = DPORT_REG_READ(DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG);
|
||||
|
||||
} else {
|
||||
#if !CONFIG_FREERTOS_UNICORE
|
||||
stat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_STATUS_REG);
|
||||
pid = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PID_REG);
|
||||
inst = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGINST_REG);
|
||||
@@ -482,9 +598,25 @@ static void wdt_reset_info_dump(int cpu)
|
||||
lsstat = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0STAT_REG);
|
||||
lsaddr = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0ADDR_REG);
|
||||
lsdata = DPORT_REG_READ(DPORT_APP_CPU_RECORD_PDEBUGLS0DATA_REG);
|
||||
#else
|
||||
ESP_LOGE(TAG, "WDT reset info: &s CPU not support!\n", cpu_name);
|
||||
return;
|
||||
#endif
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
stat = 0xdeadbeef;
|
||||
pid = 0;
|
||||
inst = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGINST);
|
||||
dstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS);
|
||||
data = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGDATA);
|
||||
pc = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGPC);
|
||||
lsstat = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT);
|
||||
lsaddr = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR);
|
||||
lsdata = REG_READ(ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA);
|
||||
#endif
|
||||
|
||||
if (DPORT_RECORD_PDEBUGINST_SZ(inst) == 0 &&
|
||||
DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
|
||||
DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(dstat) == DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI) {
|
||||
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x (waiti mode)", cpu_name, pc);
|
||||
} else {
|
||||
ESP_LOGW(TAG, "WDT reset info: %s CPU PC=0x%x", cpu_name, pc);
|
||||
@@ -506,21 +638,31 @@ static void wdt_reset_check(void)
|
||||
RESET_REASON rst_reas[2];
|
||||
|
||||
rst_reas[0] = rtc_get_reset_reason(0);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
rst_reas[1] = rtc_get_reset_reason(1);
|
||||
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
|
||||
rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
|
||||
rst_reas[0] == TGWDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
|
||||
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
if (rst_reas[1] == RTCWDT_SYS_RESET || rst_reas[1] == TG0WDT_SYS_RESET || rst_reas[1] == TG1WDT_SYS_RESET ||
|
||||
rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET) {
|
||||
rst_reas[1] == TGWDT_CPU_RESET || rst_reas[1] == RTCWDT_CPU_RESET) {
|
||||
ESP_LOGW(TAG, "APP CPU has been reset by WDT.");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
#elif CONFIG_IDF_TARGET_ESP32S2BETA
|
||||
if (rst_reas[0] == RTCWDT_SYS_RESET || rst_reas[0] == TG0WDT_SYS_RESET || rst_reas[0] == TG1WDT_SYS_RESET ||
|
||||
rst_reas[0] == TG0WDT_CPU_RESET || rst_reas[0] == TG1WDT_CPU_RESET || rst_reas[0] == RTCWDT_CPU_RESET) {
|
||||
ESP_LOGW(TAG, "PRO CPU has been reset by WDT.");
|
||||
wdt_rst = 1;
|
||||
}
|
||||
#endif
|
||||
if (wdt_rst) {
|
||||
// if reset by WDT dump info from trace port
|
||||
wdt_reset_info_dump(0);
|
||||
#if CONFIG_IDF_TARGET_ESP32
|
||||
wdt_reset_info_dump(1);
|
||||
#endif
|
||||
}
|
||||
wdt_reset_cpu0_info_enable();
|
||||
}
|
||||
@@ -528,7 +670,7 @@ static void wdt_reset_check(void)
|
||||
void __assert_func(const char *file, int line, const char *func, const char *expr)
|
||||
{
|
||||
ESP_LOGE(TAG, "Assert failed in %s, %s:%d (%s)", func, file, line, expr);
|
||||
while(1) {}
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
void abort()
|
||||
@@ -539,5 +681,5 @@ void abort()
|
||||
if (esp_cpu_in_ocd_debug_mode()) {
|
||||
__asm__ ("break 0,0");
|
||||
}
|
||||
while(1) {}
|
||||
while (1) {}
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user