alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-09-25 17:52:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

bootloader_support: add esp32-s3 initial support

Browse Source
This commit is contained in:
morris
2020-07-29 22:03:46 +08:00
parent b845bb5787
commit 6225932201
36 changed files with 1550 additions and 77 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
components/bootloader_support/src/bootloader_flash.c
View File

@@ -32,7 +32,9 @@
#endif
#if CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/spi_flash.h" //For SPI_Encrypt_Write
#include "esp32s2/rom/spi_flash.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#endif
@@ -87,7 +89,7 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool
if (write_encrypted) {
#if CONFIG_IDF_TARGET_ESP32
return spi_flash_write_encrypted(dest_addr, src, size);
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
return SPI_Encrypt_Write(dest_addr, src, size);
#endif
} else {
@@ -115,6 +117,10 @@ esp_err_t bootloader_flash_erase_range(uint32_t start_addr, uint32_t size)
#include "esp32s2/rom/spi_flash.h"
#include "esp32s2/rom/cache.h"
#include "soc/cache_memory.h"
#elif CONFIG_IDF_TARGET_ESP32S3
#include "esp32s3/rom/spi_flash.h"
#include "esp32s3/rom/cache.h"
#include "soc/cache_memory.h"
#endif
static const char *TAG = "bootloader_flash";
@@ -126,7 +132,7 @@ static const char *TAG = "bootloader_flash";
#define MMU_SIZE (0x320000)
#define MMU_BLOCK50_VADDR (MMU_BLOCK0_VADDR + MMU_SIZE)
#define FLASH_READ_VADDR MMU_BLOCK50_VADDR
#elif CONFIG_IDF_TARGET_ESP32S2
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
/* Use first 63 blocks in MMU for bootloader_mmap,
63th block for bootloader_flash_read
*/
@@ -171,6 +177,9 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
#elif CONFIG_IDF_TARGET_ESP32S2
uint32_t autoload = Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
#elif CONFIG_IDF_TARGET_ESP32S3
uint32_t autoload = Cache_Suspend_DCache();
Cache_Invalidate_DCache_All();
#endif
ESP_LOGD(TAG, "mmu set paddr=%08x count=%d size=%x src_addr=%x src_addr_aligned=%x",
src_addr & MMU_FLASH_MASK, count, size, src_addr, src_addr_aligned );
@@ -178,6 +187,8 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
int e = cache_flash_mmu_set(0, 0, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count);
#elif CONFIG_IDF_TARGET_ESP32S2
int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
#elif CONFIG_IDF_TARGET_ESP32S3
int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK0_VADDR, src_addr_aligned, 64, count, 0);
#endif
if (e != 0) {
ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
@@ -185,6 +196,8 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
Cache_Read_Enable(0);
#elif CONFIG_IDF_TARGET_ESP32S2
Cache_Resume_ICache(autoload);
#elif CONFIG_IDF_TARGET_ESP32S3
Cache_Resume_DCache(autoload);
#endif
return NULL;
}
@@ -192,6 +205,8 @@ const void *bootloader_mmap(uint32_t src_addr, uint32_t size)
Cache_Read_Enable(0);
#elif CONFIG_IDF_TARGET_ESP32S2
Cache_Resume_ICache(autoload);
#elif CONFIG_IDF_TARGET_ESP32S3
Cache_Resume_DCache(autoload);
#endif
mapped = true;
@@ -212,6 +227,11 @@ void bootloader_munmap(const void *mapping)
Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
Cache_MMU_Init();
#elif CONFIG_IDF_TARGET_ESP32S3
//TODO, save the autoload value.
Cache_Suspend_DCache();
Cache_Invalidate_DCache_All();
Cache_MMU_Init();
#endif
mapped = false;
current_read_mapping = UINT32_MAX;
@@ -239,12 +259,16 @@ static esp_err_t bootloader_flash_read_no_decrypt(size_t src_addr, void *dest, s
Cache_Flush(0);
#elif CONFIG_IDF_TARGET_ESP32S2
uint32_t autoload = Cache_Suspend_ICache();
#elif CONFIG_IDF_TARGET_ESP32S3
uint32_t autoload = Cache_Suspend_DCache();
#endif
esp_rom_spiflash_result_t r = esp_rom_spiflash_read(src_addr, dest, size);
#if CONFIG_IDF_TARGET_ESP32
Cache_Read_Enable(0);
#elif CONFIG_IDF_TARGET_ESP32S2
Cache_Resume_ICache(autoload);
#elif CONFIG_IDF_TARGET_ESP32S3
Cache_Resume_DCache(autoload);
#endif
return spi_to_esp_err(r);
@@ -266,12 +290,17 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
#elif CONFIG_IDF_TARGET_ESP32S2
uint32_t autoload = Cache_Suspend_ICache();
Cache_Invalidate_ICache_All();
#elif CONFIG_IDF_TARGET_ESP32S3
uint32_t autoload = Cache_Suspend_DCache();
Cache_Invalidate_DCache_All();
#endif
ESP_LOGD(TAG, "mmu set block paddr=0x%08x (was 0x%08x)", map_at, current_read_mapping);
#if CONFIG_IDF_TARGET_ESP32
int e = cache_flash_mmu_set(0, 0, FLASH_READ_VADDR, map_at, 64, 1);
#elif CONFIG_IDF_TARGET_ESP32S2
int e = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
#elif CONFIG_IDF_TARGET_ESP32S3
int e = Cache_Dbus_MMU_Set(MMU_ACCESS_FLASH, MMU_BLOCK63_VADDR, map_at, 64, 1, 0);
#endif
if (e != 0) {
ESP_LOGE(TAG, "cache_flash_mmu_set failed: %d\n", e);
@@ -279,6 +308,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
Cache_Read_Enable(0);
#elif CONFIG_IDF_TARGET_ESP32S2
Cache_Resume_ICache(autoload);
#elif CONFIG_IDF_TARGET_ESP32S3
Cache_Resume_DCache(autoload);
#endif
return ESP_FAIL;
}
@@ -287,6 +318,8 @@ static esp_err_t bootloader_flash_read_allow_decrypt(size_t src_addr, void *dest
Cache_Read_Enable(0);
#elif CONFIG_IDF_TARGET_ESP32S2
Cache_Resume_ICache(autoload);
#elif CONFIG_IDF_TARGET_ESP32S3
Cache_Resume_DCache(autoload);
#endif
}
map_ptr = (uint32_t *)(FLASH_READ_VADDR + (word_src - map_at));
@@ -342,8 +375,8 @@ esp_err_t bootloader_flash_write(size_t dest_addr, void *src, size_t size, bool
if (write_encrypted) {
#if CONFIG_IDF_TARGET_ESP32
return spi_to_esp_err(esp_rom_spiflash_write_encrypted(dest_addr, src, size));
#elif CONFIG_IDF_TARGET_ESP32S2
// TODO: use the same ROM AP here
#elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
// TODO: use the same ROM API here
return spi_to_esp_err(SPI_Encrypt_Write(dest_addr, src, size));
#endif
} else {