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feat(parlio_rx): support parlio rx on p4
This commit is contained in:

committed by
Kevin (Lao Kaiyao)

parent
d3abfa3d73
commit
627631429a
@@ -63,6 +63,10 @@ config SOC_ETM_SUPPORTED
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bool
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default y
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config SOC_PARLIO_SUPPORTED
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bool
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default y
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config SOC_ASYNC_MEMCPY_SUPPORTED
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bool
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default y
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@@ -987,6 +991,10 @@ config SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH
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int
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default 16
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config SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT
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bool
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default y
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config SOC_PARLIO_TX_SIZE_BY_DMA
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bool
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default y
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@@ -635,8 +635,8 @@ typedef enum {
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*/
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typedef enum {
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PARLIO_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
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PARLIO_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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PARLIO_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */
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PARLIO_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the source clock */
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PARLIO_CLK_SRC_EXTERNAL = -1, /*!< Select EXTERNAL clock as the source clock */
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PARLIO_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select PLL_F160M as the default clock choice */
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} soc_periph_parlio_clk_src_t;
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@@ -34,7 +34,7 @@
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#define SOC_MCPWM_SUPPORTED 1
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#define SOC_TWAI_SUPPORTED 1
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#define SOC_ETM_SUPPORTED 1
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// #define SOC_PARLIO_SUPPORTED 1 //TODO: IDF-7471
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#define SOC_PARLIO_SUPPORTED 1
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#define SOC_ASYNC_MEMCPY_SUPPORTED 1
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#define SOC_EMAC_SUPPORTED 1
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#define SOC_USB_OTG_SUPPORTED 1
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@@ -394,6 +394,7 @@
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#define SOC_PARLIO_RX_UNITS_PER_GROUP 1U /*!< number of RX units in each group */
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#define SOC_PARLIO_TX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the TX unit */
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#define SOC_PARLIO_RX_UNIT_MAX_DATA_WIDTH 16 /*!< Number of data lines of the RX unit */
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#define SOC_PARLIO_RX_CLK_SUPPORT_OUTPUT 1 /*!< Support output RX clock to a GPIO */
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#define SOC_PARLIO_TX_SIZE_BY_DMA 1 /*!< Transaction length is controlled by DMA instead of indicated by register */
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/*--------------------------- MPI CAPS ---------------------------------------*/
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