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Merge branch 'feature/c3_mbedtls_merge' into 'master'
mbedtls: merge changes from C3 to master Closes IDF-2544 and IDF-2114 See merge request espressif/esp-idf!11718
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@@ -1,26 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define SOC_RSA_MAX_BIT_LEN (3072)
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#ifdef __cplusplus
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}
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#endif
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@@ -1,54 +0,0 @@
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// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* ESP32 style SHA engine, where multiple states can be stored in parallel */
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#define SOC_SHA_SUPPORT_PARALLEL_ENG (0)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has "crypto DMA", which is shared with AES */
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#define SOC_SHA_CRYPTO_DMA (0)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GENERAL_DMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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#define SOC_SHA_SUPPORT_SHA384 (0)
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#define SOC_SHA_SUPPORT_SHA512 (0)
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#define SOC_SHA_SUPPORT_SHA512_224 (0)
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#define SOC_SHA_SUPPORT_SHA512_256 (0)
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#define SOC_SHA_SUPPORT_SHA512_T (0)
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#ifdef __cplusplus
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}
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#endif
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@@ -11,6 +11,7 @@
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// There are 3 DMA channels on ESP32-C3
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// Attention: These fixed DMA channels are temporarily workaround before we have a centralized DMA controller API to help alloc the channel dynamically
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// Remove them when GDMA driver API is ready
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#define SOC_GDMA_AES_DMA_CHANNEL (0)
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#define SOC_GDMA_M2M_DMA_CHANNEL (0)
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#define SOC_GDMA_SHA_DMA_CHANNEL (1)
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#define SOC_GDMA_SPI2_DMA_CHANNEL (2)
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@@ -27,7 +28,6 @@
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#include "dac_caps.h"
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#include "i2c_caps.h"
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#include "mpu_caps.h"
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#include "rsa_caps.h"
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#include "sigmadelta_caps.h"
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#include "systimer_caps.h"
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#include "uart_caps.h"
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@@ -41,7 +41,6 @@
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#include "gpio_caps.h"
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#include "ledc_caps.h"
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#include "rmt_caps.h"
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#include "sha_caps.h"
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#include "spi_caps.h"
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#include "uart_caps.h"
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#include "int_caps.h"
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@@ -49,9 +48,6 @@
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/*-------------------------- TOUCH SENSOR CAPS -------------------------------*/
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#define SOC_TOUCH_SENSOR_NUM (0) /*! No touch sensors on ESP32-C3 */
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/*-------------------------- ADC CAPS -------------------------------*/
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#define SOC_ADC_PERIPH_NUM (2)
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#define SOC_ADC_PATT_LEN_MAX (16)
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#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) ((PERIPH_NUM==0)? 5 : 1)
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#define SOC_ADC_MAX_CHANNEL_NUM (10)
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@@ -64,6 +60,32 @@
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*/
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#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) 1
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/*--------------------------- SHA CAPS ---------------------------------------*/
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/* Max amount of bytes in a single DMA operation is 4095,
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for SHA this means that the biggest safe amount of bytes is
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31 blocks of 128 bytes = 3968
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*/
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#define SOC_SHA_DMA_MAX_BUFFER_SIZE (3968)
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#define SOC_SHA_SUPPORT_DMA (1)
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/* The SHA engine is able to resume hashing from a user */
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#define SOC_SHA_SUPPORT_RESUME (1)
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/* Has a centralized DMA, which is shared with all peripherals */
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#define SOC_SHA_GENERAL_DMA (1)
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/* Supported HW algorithms */
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#define SOC_SHA_SUPPORT_SHA1 (1)
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#define SOC_SHA_SUPPORT_SHA224 (1)
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#define SOC_SHA_SUPPORT_SHA256 (1)
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/*--------------------------- RSA CAPS ---------------------------------------*/
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#define SOC_RSA_MAX_BIT_LEN (3072)
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/*-------------------------- AES CAPS -----------------------------------------*/
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#define SOC_AES_SUPPORT_DMA (1)
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